JPS59229849A - Power transistor - Google Patents
Power transistorInfo
- Publication number
- JPS59229849A JPS59229849A JP58105225A JP10522583A JPS59229849A JP S59229849 A JPS59229849 A JP S59229849A JP 58105225 A JP58105225 A JP 58105225A JP 10522583 A JP10522583 A JP 10522583A JP S59229849 A JPS59229849 A JP S59229849A
- Authority
- JP
- Japan
- Prior art keywords
- base
- emitter
- transistor
- terminal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は半導体片上に設けられた電極と沓端子導体の間
が細い導線によって接続されており、ベース、エミッタ
間にベース駆動回路を接続して使用される電力用トラン
ジスタに関する。[Detailed Description of the Invention] [Technical Field to Which the Invention Pertains] The present invention relates to a semiconductor device in which an electrode provided on a semiconductor piece and a foot terminal conductor are connected by a thin conducting wire, and a base drive circuit is connected between a base and an emitter. The present invention relates to power transistors used in
電力用トランジスタをモータ制御等のインバータ回路あ
るいはＣＶＣＦ電源用スイッチング回路に適用した場合
、何らかの原因によってトランジスタが破壊するとそれ
によってトランジスタのべ ゛−ス駆動回路の破壊
を招くことがある。第１図に示すモータ２を制御するイ
ンバータ回路において、トランジスタ１１．１４は同時
にオン、オフするものとする。またトランジスタ１３．
１２も同時ニオ・ン、オフするものとする。さらにトラ
ンジス反
り１１，１４と１３．１２は相互するオン、オフ動作を
するものとする。いま、仮にトランジスタ１４が破壊し
、その状態でトランジスター２゜１３がオン状態になっ
たとすると、トランジスタ１２には多大の電流が流れる
のでトランジスタ１２も破壊に至る場合がある。When a power transistor is applied to an inverter circuit for motor control or the like or a switching circuit for a CVCF power supply, if the transistor is destroyed for some reason, the base drive circuit of the transistor may be destroyed. In the inverter circuit that controls the motor 2 shown in FIG. 1, it is assumed that transistors 11 and 14 are turned on and off at the same time. Also, transistor 13.
12 is also turned on and off at the same time. Furthermore, it is assumed that the transistor warps 11, 14 and 13.12 perform mutual on/off operations. Now, if the transistor 14 is destroyed and the transistor 2.13 is turned on in that state, a large amount of current will flow through the transistor 12, which may lead to the destruction of the transistor 12 as well.
トランジスタ１１．１２の双方が破壊すると電源コンデ
ンサ３からトランジスタ１１．１２を経てコンデンサ３
に至る電流Ｉｌが流れる。この結果第２図に示すトラン
ジスタチップ１のエミッタとエミッタ端子４を接続する
通常アルミニウムからなる導線５が焼損し、オープンモ
ードとなる。この状態を示すのが第３図である。すなわ
ちエミッタ接続導線５がオープンになると、電源コンデ
ンサ３の高電圧がトランジスタ１１のコレクタ→ペース
→ベース駆動回路６→トランジスタ１２→コンデンサ３
とすわる電流■２を流して、ベース駆動回路６を破壊さ
せてし丈う。これを防止するために従来は第４図、第５
図のような方法がとられていた。第４図に示す方法は、
電源とトランジスタ１１〜１４の間にヒユーズ７をそう
人し、ヒユーズ７の溶断Ｉｔ値をエミッタ接続導線の溶
断Ｉ２を値より小さくすることでエミッタ接続導線がオ
ープンになる前に主回路電圧をインバータ回路から切り
離すものである。しかしながら入手できるヒユーズ７は
、トランジスタのエミッタ接続導線としてのアルミニウ
ム線などの溶断Ｉｔ値を考慮して作られたものでないか
ら、その協調は難しく、協調のとれない場合もある。第
５図においては、トランジスタ１１〜１４のベース端子
とベース駆動回路の間にそれぞれヒユーズ８が挿入され
、またヒユーズ８の駆動回路側とエミッタ端子の間に直
列接続された二つのダイオード９がエミッタ接合に順並
列に接続されていて、ダイオード９の破壊Ｉｔ［ヒユー
ズ８の溶断Ｉｔ値より大きくすることにより、ダイオー
ド９の順電圧ｖＦの２倍以上の電圧がベース回路に加わ
ることを無くした方法である。しかしこの方法もトラン
ジスタの使用者側でヒユーズの選択、ヒユーズ、ダイオ
ードの接、続等のわずられしさがある。If both transistors 11 and 12 are destroyed, the power supply capacitor 3 passes through transistors 11 and 12 to capacitor 3.
A current Il flows. As a result, the conductive wire 5, which is usually made of aluminum and connects the emitter of the transistor chip 1 and the emitter terminal 4 shown in FIG. 2, is burnt out and becomes in an open mode. FIG. 3 shows this state. That is, when the emitter connecting conductor 5 becomes open, the high voltage of the power supply capacitor 3 is transferred from the collector of the transistor 11 to the base drive circuit 6 to the transistor 12 to the capacitor 3.
The base drive circuit 6 is destroyed by causing a current 2 to flow. In order to prevent this, conventionally, the
The method shown in the figure was used. The method shown in Figure 4 is
By placing fuse 7 between the power supply and transistors 11 to 14, and making the fuse 7's blowout value smaller than the emitter connection conductor's blowout I2 value, the main circuit voltage can be inverted before the emitter connection conductor becomes open. It is separated from the circuit. However, the available fuses 7 are not made with consideration to the fusing It value of an aluminum wire or the like as an emitter connection conductor of a transistor, and therefore it is difficult to coordinate them, and there are cases where coordination cannot be achieved. In FIG. 5, fuses 8 are inserted between the base terminals of transistors 11 to 14 and the base drive circuit, and two diodes 9 are connected in series between the drive circuit side of the fuses 8 and the emitter terminal. A method that prevents a voltage that is more than twice the forward voltage vF of diode 9 from being applied to the base circuit by increasing the value of diode 9's breakdown It [fuse 8's blowing It] which is connected in order and parallel to the junction. It is. However, this method also requires the user of the transistor to be troublesome in selecting the fuse, connecting the fuse and the diode, etc.
本発明は上述の欠点を除き、エミッタの接続導線の断線
に基づくベース駆動回路の損傷を避ける方法について使
用者側で全く考慮する必要のない電力用トランジスタを
提供することを目的とする。The object of the present invention is to eliminate the above-mentioned disadvantages and to provide a power transistor in which the user does not have to consider at all how to avoid damage to the base drive circuit due to disconnection of the emitter connecting conductor.
本発明は、電力用トランジスタのパッケージ内において
ベース端子とエミッタ端子との間に、エミッタ接合に順
並列で、オン状態での電圧降下がベース、エミッタ間飽
和電圧より大きく、また駆動回路破壊電圧以下であり、
その破壊Ｉ２を値がベース接続導線の溶断Ｉｔ値より大
きいダイオードまたはスイッチング素子を挿入すること
によって上記の目的を達成する。The present invention provides a voltage drop between a base terminal and an emitter terminal in a power transistor package in order and parallel to the emitter junction, which is larger than the saturation voltage between the base and emitter, and lower than the drive circuit breakdown voltage. and
The above object is achieved by inserting a diode or a switching element whose destruction I2 value is larger than the melting It value of the base connecting conductor.
第６図は本発明の一実施例を示し、電力用ＰＮＰトラン
ジスタのコレクタ端子となる銅基板１０上に固着された
トランジスタチップ１のエミッタ電極はアルミニウム線
５によってエミッタ端子４と接続されている。このエミ
ッタ端子４とベース電極にアルミニウム線２１によって
接続されたベース端子２２の間に本発明により直列接続
された二つのダイオード３１がそう人されている。この
ダイオードは、その破壊Ｉｔ値はベース接続導線２１の
溶断Ｉｔ値より必ず大きく、また短絡モード破壊するも
のが奸才しい。ダイオード３１の代りに、エミッタ、ベ
ース間に第７図ないし第１Ｏ図に示したように、アノー
ド、ゲート間にダイオード３０が並列接続されたサイリ
スタ３２、コレクタ、ベース間にダイオード３０が並列
接続されたトランジスタ３３、ソース、ゲート間に二つ
の直列接続ダイオード３０が並列接続されたＦＥＴ３４
、あるいは逆直列接続されたツェナダイオード３５を挿
入してもよい。これらの素子を含む挿入回路の電圧降下
は、トランジスタのベース、エミッタ間飽和電圧よりも
高く、ベース駆動回路が破壊する電圧より小さいことを
必要とする。これによって第５図の回路と同様に挿入回
路の電圧降下以上の電圧がベース駆動回路に加わること
がなく、たとえ過電流が流れてもベース回路の破壊以前
にベース接続導線２１が溶断し、てし才う。FIG. 6 shows an embodiment of the present invention, in which an emitter electrode of a transistor chip 1 fixed on a copper substrate 10, which serves as a collector terminal of a power PNP transistor, is connected to an emitter terminal 4 by an aluminum wire 5. According to the invention, two diodes 31 are connected in series between the emitter terminal 4 and the base terminal 22 connected to the base electrode by an aluminum wire 21. The breakdown It value of this diode is always greater than the melting It value of the base connecting conductor 21, and it is clever that it breaks down in the short circuit mode. Instead of the diode 31, a thyristor 32 has a diode 30 connected in parallel between the anode and the gate, and a diode 30 is connected in parallel between the collector and the base, as shown in FIGS. 7 to 1O between the emitter and the base. FET 34 in which two series-connected diodes 30 are connected in parallel between the transistor 33, the source, and the gate.
Alternatively, a Zener diode 35 connected in anti-series may be inserted. The voltage drop of the inserted circuit including these elements needs to be higher than the saturation voltage between the base and emitter of the transistor and lower than the voltage that destroys the base drive circuit. As a result, as with the circuit shown in Fig. 5, a voltage higher than the voltage drop of the insertion circuit is not applied to the base drive circuit, and even if an overcurrent flows, the base connecting conductor 21 will melt before the base circuit is destroyed. I'm talented.
トランジスタチップ１右よび各付属素子３０〜３５は、
例えば樹脂注型により、基板１０の下面、エミッタ端子
４、ベース端子２２のそれぞれの先端を露出させてパッ
ケージ２３内に封止される。The right side of the transistor chip 1 and each attached element 30 to 35 are as follows:
For example, by resin casting, the lower surface of the substrate 10, the tips of each of the emitter terminal 4 and the base terminal 22 are exposed and sealed in the package 23.
本発明は電力用トランジスタの駆動回路の破壊を防止す
るためにトランジスタのベース、エミッタ間にそう入さ
れるダイオードまたはスイッチング素子をトランジスタ
を同一のパッケージ内に組み込んだもので、電力用トラ
ンジスタをプリッジ結線した場合に、過大な電流が流れ
ることによるベース駆動回路の破壊からの保護を、使用
者側で特に考慮する必要がなく、電力用トランジスタの
使用者に多大の便を与えるものである。The present invention incorporates a diode or a switching element inserted between the base and emitter of the transistor in the same package to prevent damage to the drive circuit of the power transistor, and the power transistor is bridge-connected. In this case, there is no need for the user to particularly consider protection of the base drive circuit from destruction due to excessive current flowing, which provides great convenience to the user of the power transistor.
第１図は電力用トランジスタを用いたインバータの回路
図、第２図は従来の電力用トランジスタの構造の斜視図
、第３図は８１図のインバータにおけるエミッタ導線断
線時の状態を示す回路図、第４図、第５図は従来使用者
で行われていたトランジスタ駆動回路の保護策の二つの
例をそれぞれ示す回路図、第６図は本発明の一実施例の
斜視図、第７図ないし第１０図はそれぞれ異なる実施例
を宗す回路図である。
１・・・トランジスタチップ、４・・・エミッタ端子、
２１・・・ベース接続導線、２２・・・ベース端子、２
３・・・パッケージ、３０．３１・・・ダイオード、３
２・・・サイリスタ、３３・・・トランジスタ、第１図
第２図
一犯
第４図
叫「
第５図FIG. 1 is a circuit diagram of an inverter using power transistors, FIG. 2 is a perspective view of the structure of a conventional power transistor, and FIG. 3 is a circuit diagram showing the state of the inverter shown in FIG. 81 when the emitter conductor is disconnected. 4 and 5 are circuit diagrams showing two examples of protective measures for transistor drive circuits conventionally taken by users, FIG. 6 is a perspective view of an embodiment of the present invention, and FIGS. FIG. 10 is a circuit diagram showing different embodiments. 1...Transistor chip, 4...Emitter terminal,
21...Base connection conductor, 22...Base terminal, 2
3...Package, 30.31...Diode, 3
2... Thyristor, 33... Transistor, Fig. 1 Fig. 2 Fig. 1 Criminal Fig. 4 Scream Fig. 5
Claims (1)
線によって接続されており、ベース、エミッタ間に駆動
回路を接続して使用されるものにおいて、同一パッケー
ジ内においてベース端子とエミッタ端子の間に、エミッ
タ接合に順並列で、オン状態での電圧降下がベース、エ
ミッタ間飽和電圧より大きく、才た駆動回路破壊電圧以
下であり、その破壊Ｉｔ値がベース接続導線の溶断Ｉｔ
値より大きいダイオードオたはスイッチング素子が挿入
されたことを特徴とする電力用トランジスタ。1) In devices in which the electrodes provided on the semiconductor chip and each terminal are connected by thin conductive wires, and a drive circuit is connected between the base and emitter, the base terminal and emitter terminal can be connected in the same package. In between, in parallel to the emitter junction, the voltage drop in the on state is greater than the saturation voltage between the base and emitter, and is less than the breakdown voltage of the active drive circuit, and the breakdown It value is equal to the melting It of the base connecting conductor.
A power transistor characterized by having a diode or a switching element inserted therein which has a larger value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58105225A JPS59229849A (en) | 1983-06-13 | 1983-06-13 | Power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58105225A JPS59229849A (en) | 1983-06-13 | 1983-06-13 | Power transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59229849A true JPS59229849A (en) | 1984-12-24 |
Family
ID=14401718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58105225A Pending JPS59229849A (en) | 1983-06-13 | 1983-06-13 | Power transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59229849A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63239854A (en) * | 1986-11-28 | 1988-10-05 | Fuji Electric Co Ltd | Overcurrent limiting type semiconductor device |
| US4920405A (en) * | 1986-11-28 | 1990-04-24 | Fuji Electric Co., Ltd. | Overcurrent limiting semiconductor device |
-
1983
- 1983-06-13 JP JP58105225A patent/JPS59229849A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63239854A (en) * | 1986-11-28 | 1988-10-05 | Fuji Electric Co Ltd | Overcurrent limiting type semiconductor device |
| US4920405A (en) * | 1986-11-28 | 1990-04-24 | Fuji Electric Co., Ltd. | Overcurrent limiting semiconductor device |
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