JPS5922329A - Polisher for polishing of semiconductor wafer - Google Patents

Polisher for polishing of semiconductor wafer

Info

Publication number
JPS5922329A
JPS5922329A JP13260382A JP13260382A JPS5922329A JP S5922329 A JPS5922329 A JP S5922329A JP 13260382 A JP13260382 A JP 13260382A JP 13260382 A JP13260382 A JP 13260382A JP S5922329 A JPS5922329 A JP S5922329A
Authority
JP
Japan
Prior art keywords
polisher
layer
polishing
abrasive
wafers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13260382A
Other languages
Japanese (ja)
Inventor
Tsuneo Hamaguchi
浜口 恒夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13260382A priority Critical patent/JPS5922329A/en
Publication of JPS5922329A publication Critical patent/JPS5922329A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02024Mirror polishing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To obtain the semiconductor wafer having favorable precision of the shape and having the mirror surface of no distortion by a method wherein the polisher is consisting of two layer structure of a polishing layer and an elastic body layer. CONSTITUTION:The semiconductor wafers 1 adhered to an adhesive surface plate 2 are sticked to a polishing surface plate 6 consisting of a rotary disk, and polishing is performed rotating in the directions shown with arrow marks. The polisher has the concave parts enabled to hold an abrasive, and has two layer strcture consisting of the polishing layer 4 of the soft quality of material of 70 or less at a rubber hardness meter and the elastic body layer 5 of the hard quality of material of 80 or more at the rubber hardness meter. The lubricous layers 3 of the abrasive are generated between the semiconductor wafers 1 and the polishing layer 4 of the polisher, and uncontactingly polish the semiconductor wafers 1. Even when the semiconductor wafers 1 come in contact with the polishing layer 4 of the polisher during the process of polishing, no scratch is generated on the surfaces of the wafers because the polishing layer 4 is soft. Moreover because the elastic body layer 5 is hard, and no sinking of the wafers 1 in the polisher is generated, deterioration of flatness of the wafers 1 is not generated.

Description

【発明の詳細な説明】 本発明は半導体ウェハの表面を高精度でかつ無歪鏡面に
仕上げるために用いる研摩ポリシャに関するものである
。ポリシング加工はLSI用シリコンウェハ研摩加工の
最終工程であシ、ウエノ・を無歪鏡面に仕上げることを
目的として行なわれ、100〜2001程度の微粒子を
PH9〜12程度のアルカリ水溶液に懸濁したボリシン
グ液で、回転円板上に設けられたポリウレタン等を材質
とするポリシャで半導体ウエノ・を研摩する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a polishing polisher used for finishing the surface of a semiconductor wafer with high precision and a distortion-free mirror surface. Polishing is the final process of polishing silicon wafers for LSI, and is performed with the aim of finishing Ueno to a distortion-free mirror surface. It is a polishing process in which fine particles of about 100 to 2001 are suspended in an alkaline aqueous solution with a pH of about 9 to 12. The semiconductor wafer is polished using a polisher made of polyurethane or the like, which is mounted on a rotating disk.

従来から、半導体ウエノ・の平面度を高精度にするには
、ウェハのポリシャへの沈みこみの小さいつまシ硬いポ
リシャが適当であシ、無歪鏡面にするには軟かいポリシ
ャが適当であると考えられてきた。つまシ半導体ウェハ
の形状精度を良好にすることと、無歪鏡面にすることは
相反する要求であった。
Conventionally, in order to achieve high precision flatness of semiconductor wafers, a hard polisher with a small tab that causes less sinking of the wafer into the polisher is appropriate, and to obtain a distortion-free mirror surface, a soft polisher is appropriate. It has been thought that Improving the shape accuracy of the pick-up semiconductor wafer and making it a distortion-free mirror surface are contradictory demands.

従って、形状精度良く、無歪鏡面のウエノ・を得るため
には、ポリシングを2回に分けて、1次ボリシングで形
状精度の良好なウエノ・を得るため、ポリシャへの沈み
こみの小さい硬いポリシャを用い、2次ポリシングでは
無歪鏡面を得るため軟いポリシャでボリシングを行なっ
ているのが現状である。しかし、2次ボリシングで軟か
いポリシャを用いたためにおこる形状精度の悪化はさけ
られないため、この2段階ボリシングでは形状精度に限
界がある。
Therefore, in order to obtain a wafer with good shape accuracy and a distortion-free mirror surface, polishing is divided into two steps, and in order to obtain a wafer with good shape precision in the first polishing, a hard polisher that does not sink into the polisher is used. Currently, secondary polishing is performed using a soft polisher to obtain a distortion-free mirror surface. However, since deterioration in shape accuracy due to the use of a soft polisher in the secondary borising cannot be avoided, there is a limit to the shape accuracy in this two-step boring.

本発明は前記欠点をなくし、形状精度良好にかつ、無歪
鏡面を得るポリシャを提供する。
The present invention eliminates the above-mentioned drawbacks and provides a polisher that provides a mirror surface with good shape accuracy and no distortion.

本発明によれば、研摩剤を保持しうる多数の凹部を表面
全体に均一に有し、ゴム#!度肝で70以下の軟質で均
一厚さの薄い研摩層の裏面に該研摩層よりもかなり硬い
(ゴム硬度計で80以上)材質からなる弾性体層を積層
し、前記研摩層と該弾性体層との2層構造からなること
を特徴とするポリシャで半導体ウェハをボリシングする
と形状精度良好で無歪鏡面の半導体ウェハを得ることが
できる。
According to the present invention, the rubber #! On the back side of a thin abrasive layer that is soft and has a uniform thickness of 70 or less, an elastic layer made of a material that is considerably harder than the abrasive layer (80 or more on a rubber hardness meter) is laminated, and the abrasive layer and the elastic layer are laminated. By polishing a semiconductor wafer with a polisher characterized by having a two-layer structure, it is possible to obtain a semiconductor wafer with good shape accuracy and a non-distorted mirror surface.

本発明のポリシャを用いたポリシング機構を明らかにす
ると、表面に研摩剤を保持しうる凹部を表面全体に均一
に有するポリシャを用いた場合のボリシング現象を注意
深く観察すると、被加工物である半導体ウェハはポリシ
ャに直接接触せず半導体ウェハとポリシャの間に研摩剤
による数μmの潤滑層ができていて、ボリシングが行な
われており、これはポリシャ表面に研摩剤を保持しうる
凹部を有するポリシャに特有の性質であることが実験的
にわかった。
Clarifying the polishing mechanism using the polisher of the present invention, when carefully observing the polisher that has concave portions uniformly over the entire surface that can hold an abrasive agent, it is possible to see that the polisher is Bolishing is performed by forming a lubricating layer of a few micrometers with abrasive between the semiconductor wafer and the polisher without making direct contact with the polisher. It was experimentally found that this is a unique property.

さらに、材質をゴム硬度計で70以下(80以上ではウ
ェハ加工面に加工歪が検出された)という軟かい材料で
構成することにより、ウェハがポリシャに衝突しても、
ウェハ面にキズの発生がなく無歪鏡面のウェハが得られ
る。
Furthermore, by using a soft material with a rubber hardness of 70 or less (with a hardness of 80 or more, processing distortion was detected on the wafer processing surface), even if the wafer collides with the polisher,
A wafer with a distortion-free mirror surface without any scratches on the wafer surface can be obtained.

また、ウェハの形状を良好にするには、ウェハノホリシ
ャへの沈みが小さいポリシャが適当テあることも実験的
に求められている。
Furthermore, in order to improve the shape of the wafer, it has been experimentally required that a polisher that sinks into the wafer polisher with a small amount is suitable.

従って、本発明は上記2つの性質を合せてもったもので
、ポリシャの表面に研摩剤を保持しうる凹部を有する軟
かい材質からなる研摩層を構成することで、半導体ウェ
ハを無歪鏡面に仕上げ、またポリシャの本体には硬い弾
性体層(ゴム硬度計で80以上)を構成することにょシ
、ウェハの平面度を良好にし、ウェハの無歪鏡面と形状
精度を同時に満足する利点を有する。
Therefore, the present invention combines the above two properties, and by forming an abrasive layer made of a soft material with recesses capable of holding an abrasive on the surface of the polisher, a semiconductor wafer can be made into a mirror-like surface without distortion. In addition, the main body of the polisher is constructed with a hard elastic layer (80 or higher on a rubber hardness meter), which has the advantage of improving the flatness of the wafer and simultaneously satisfying the wafer's distortion-free mirror surface and shape accuracy. .

以下実施例によシ詳細に説明する。This will be explained in detail below using examples.

図はボリシング状態の断面形状を示す。図に従って、半
導体ウェハのボリシングを説明する。
The figure shows the cross-sectional shape in the boring state. Boring of a semiconductor wafer will be explained according to the figures.

接着定板2に接着された半導体ウェハ1は回転円板であ
るボリシング定板6の上に貼付けされた研摩層4と弾性
体層5の2層構造からなるポリシャの上で研摩剤3を介
して矢印方向に回転しながらボリシングされる。
Semiconductor wafer 1 bonded to adhesive plate 2 is polished with abrasive 3 on a polisher consisting of a two-layer structure consisting of an abrasive layer 4 and an elastic layer 5, which is pasted on a borizing plate 6, which is a rotating disk. Boring is performed while rotating in the direction of the arrow.

研摩剤を保持しうる凹部を有し、ゴム硬度計で70以−
ドの軟かい材質で構成された研摩層4とゴム硬度計80
以上の硬い材質で構成された弾性体層5からなる2層構
造を有するポリシャで半導体ウェハ1をボリシングする
と、半導体ウェハ1とポリシャの研摩層4の間に研摩剤
3の潤滑層が発生し、半導体ウェハを非接触ボリシング
する。もし、半導体ウェハ1がボリシング中にポリシャ
の研摩層4と接触しても、ポリシャの研摩層4が軟かい
材質でできているため、半導体ウェハ面にキズの発生は
なく、無歪鏡面にボリシングすることができる。
It has a recess that can hold abrasive and has a rubber hardness of 70 or more.
Abrasive layer 4 made of soft material and rubber hardness meter 80
When the semiconductor wafer 1 is polished with a polisher having a two-layer structure consisting of the elastic layer 5 made of the hard material described above, a lubricant layer of the abrasive 3 is generated between the semiconductor wafer 1 and the polisher's polishing layer 4. Non-contact boring of semiconductor wafers. Even if the semiconductor wafer 1 comes into contact with the abrasive layer 4 of the polisher during the polisher, since the abrasive layer 4 of the polisher is made of a soft material, no scratches will occur on the semiconductor wafer surface, and the polisher can be borated to a mirror-like surface without distortion. can do.

また、ポリシャの弾性体層5が硬いため、半導体ウェハ
1のポリシャへの沈みこみがないため、半導体ウェハ1
の平面度の悪化はなく、形状精度良好で、無歪鏡面の半
導体ウェハ1を得ることができる。
In addition, since the elastic layer 5 of the polisher is hard, the semiconductor wafer 1 does not sink into the polisher.
There is no deterioration in the flatness of the semiconductor wafer 1, and it is possible to obtain a semiconductor wafer 1 with good shape accuracy and a distortion-free mirror surface.

次に本発明の実施結果を説明する。Next, the results of implementing the present invention will be explained.

ゴム硬度計で60、厚みo、41M、約60μm程度の
直径の凹部を有し、ポリウレタンおよび合成ゴムを主成
分とする材質そ構成されたポリシャの研摩層とポリウレ
タンを主成分とし、ゴム硬度計で80以上で厚み1.O
ffの硬い材質で構成されたポリシャ弾性体層の2層か
らなるポリシャで、研摩剤として粒径100〜2ooX
osto、 1pH+1ノーyルカリ溶液に懸濁したコ
ロイド状シリカを用い圧力100g/−の条件で直径1
ooIIIWIノsIウエハを10μmポリシングし、
ウェハの形状と無歪鏡面性を評価したところ、平面度は
3μmであシ、無歪性はwet酸化と5irtlエツチ
ングを用いたosチェックで評価した限シではO8F 
(oxdation inducedstacking
 fault )  の発生はみられず無歪であること
がわかった。また、従来から無歪鏡面が得られると判明
している市販のポリシャでボリシングした時は、無歪で
あるが平面度は8μmであった。
It has a concave part with a diameter of about 60 μm, a thickness of 41 m, and a polishing layer made of a material mainly composed of polyurethane and synthetic rubber. When the thickness is 80 or more, the thickness is 1. O
A polisher consisting of two layers of an elastic body layer made of a hard material of ff, and has a particle size of 100 to 2ooX as an abrasive.
Osto, using colloidal silica suspended in 1 pH + 1 nory alkali solution, under the condition of pressure 100 g/-, diameter 1
ooIIIWI NosI wafer was polished to 10 μm,
When evaluating the wafer shape and distortion-free specularity, the flatness was 3 μm, and the distortion-free property was O8F as evaluated by OS check using wet oxidation and 5irtl etching.
(oxidation induced stacking
No occurrence of faults was observed, indicating that there was no distortion. Further, when the mirror surface was polished using a commercially available polisher which has been known to produce a distortion-free mirror surface, the flatness was 8 μm although there was no distortion.

従って、本発明のポリシャを用いると、従来のポリシャ
に比べかなシ高品質のウェハが得ることができ、形状精
度と無歪鏡面性を同時に得ることができ、従来2工程で
あったポリシング工程を1工程にすることができ、生産
性にすぐれている利点を有する。
Therefore, when using the polisher of the present invention, it is possible to obtain wafers of much higher quality than with conventional polishers, and it is possible to obtain shape accuracy and distortion-free specularity at the same time. It has the advantage of being a one-step process and having excellent productivity.

まだ、本発明によるボリシングは非接触ボリシングであ
るため研摩剤を適当に選択して、他の半導体ウェハのポ
リシングにも適用できる利点も有する。
Furthermore, since the polishing according to the present invention is non-contact polishing, it also has the advantage that it can be applied to polishing other semiconductor wafers by appropriately selecting an abrasive.

【図面の簡単な説明】[Brief explanation of drawings]

図は、本発明のポリシャを用いたボリシング状態の断面
形状を示す図である。 図中1は半導体ウェハ、2は半導体ウェハの接着定板、
3は研摩剤、4はポリシャの研摩層、5はポリシャの弾
性体層、6はボリシング定板である。 119
The figure is a diagram showing a cross-sectional shape in a boring state using the polisher of the present invention. In the figure, 1 is a semiconductor wafer, 2 is an adhesive plate for the semiconductor wafer,
3 is an abrasive, 4 is a polishing layer of the polisher, 5 is an elastic layer of the polisher, and 6 is a polishing plate. 119

Claims (1)

【特許請求の範囲】[Claims] ゴム硬度計で70以下の軟質で均一厚さであって、研摩
剤を保持しうるようその研摩面に多数の凹部を均一に有
して成る薄い研摩層に対して、その裏面に、該研摩層よ
シも硬い(ゴム硬度計で80以上)拐質からなる弾性体
層を積層し、前記研摩層と該弾性体層との2層構造から
なることを特徴とする半導体ウエノ・の研摩用ポリシャ
A thin abrasive layer, which is soft and has a uniform thickness of 70 or less on a rubber hardness meter, and has many concave portions uniformly on its abrasive surface to hold an abrasive, is coated on the back side of the abrasive layer. For polishing a semiconductor wafer, characterized in that it has a two-layer structure of the abrasive layer and the elastic layer, in which elastic layers made of particles are laminated and each layer is hard (80 or more on a rubber hardness test). Polisha.
JP13260382A 1982-07-29 1982-07-29 Polisher for polishing of semiconductor wafer Pending JPS5922329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13260382A JPS5922329A (en) 1982-07-29 1982-07-29 Polisher for polishing of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13260382A JPS5922329A (en) 1982-07-29 1982-07-29 Polisher for polishing of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5922329A true JPS5922329A (en) 1984-02-04

Family

ID=15085192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13260382A Pending JPS5922329A (en) 1982-07-29 1982-07-29 Polisher for polishing of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5922329A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0185767A1 (en) * 1984-05-29 1986-07-02 MITSUI TOATSU CHEMICALS, Inc. Film for machining wafers
JPS6248023A (en) * 1985-08-28 1987-03-02 Shibayama Kikai Kk Clothless polishing method of semiconductor wafer
JPH0262040A (en) * 1988-08-27 1990-03-01 Nippon Steel Corp Mirror face processing of si wafer
JPH02312114A (en) * 1989-05-10 1990-12-27 Heyco Molded Prod Inc Dutomdtic fixed tewsion relaxind busing for variable panel,and its assembung metisod
EP0658401A1 (en) * 1993-12-14 1995-06-21 Shin-Etsu Handotai Company Limited Polishing member and wafer polishing apparatus
EP0845328A3 (en) * 1996-11-29 1998-12-23 Sumitomo Metal Industries, Ltd. Polishing pad and apparatus for polishing a semiconductor wafer
JP2012089599A (en) * 2010-10-18 2012-05-10 Jsr Corp Chemical mechanical polishing pad and chemical mechanical polishing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0185767A1 (en) * 1984-05-29 1986-07-02 MITSUI TOATSU CHEMICALS, Inc. Film for machining wafers
EP0185767A4 (en) * 1984-05-29 1987-09-02 Mitsui Toatsu Chemicals Film for machining wafers.
JPS6248023A (en) * 1985-08-28 1987-03-02 Shibayama Kikai Kk Clothless polishing method of semiconductor wafer
JPH0262040A (en) * 1988-08-27 1990-03-01 Nippon Steel Corp Mirror face processing of si wafer
JPH02312114A (en) * 1989-05-10 1990-12-27 Heyco Molded Prod Inc Dutomdtic fixed tewsion relaxind busing for variable panel,and its assembung metisod
EP0658401A1 (en) * 1993-12-14 1995-06-21 Shin-Etsu Handotai Company Limited Polishing member and wafer polishing apparatus
EP0845328A3 (en) * 1996-11-29 1998-12-23 Sumitomo Metal Industries, Ltd. Polishing pad and apparatus for polishing a semiconductor wafer
US6077153A (en) * 1996-11-29 2000-06-20 Sumitomo Metal Industries, Limited Polishing pad and apparatus for polishing a semiconductor wafer
JP2012089599A (en) * 2010-10-18 2012-05-10 Jsr Corp Chemical mechanical polishing pad and chemical mechanical polishing method

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