JPS59219006A - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JPS59219006A
JPS59219006A JP9432183A JP9432183A JPS59219006A JP S59219006 A JPS59219006 A JP S59219006A JP 9432183 A JP9432183 A JP 9432183A JP 9432183 A JP9432183 A JP 9432183A JP S59219006 A JPS59219006 A JP S59219006A
Authority
JP
Japan
Prior art keywords
input
voltage
circuit device
channel
output characteristic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9432183A
Other languages
Japanese (ja)
Inventor
Koichi Matsunaga
晃一 松永
Kiyoshi Imai
今井 浄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9432183A priority Critical patent/JPS59219006A/en
Publication of JPS59219006A publication Critical patent/JPS59219006A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To set a sweep time effectively by adding a circuit correcting a nonlinear input/output characteristic into a nearly linear input/output characteristic to a device having a nonlinear input/output characteristic. CONSTITUTION:Figure shows a correcting circuit, where the resistance value of resistors 21, 22 is selected equal as R1, the resistance value of resistors 23, 24 is selected equal as R2 and the resistance value of a resistor 27 is selected as R3. Further, a voltage of reference voltage terminals 8, 9 is taken as VREF1, VREF2 and the relation of them is selected as VREF1<VREF2. A voltage gain n1 when an input voltage VIN impressed to an input terminal 4 is nearly equal to VREF1 is expressed as n1=R3/2.R1. Further, a voltage gain n2 when the voltage VIN is increased more and nearly equal to the voltage VREF2 is expressed as n2=R3/ 2.R1+R3/2.R2. Thus, in selecting R1=1.5kohm, R2=0.75kohm, and R3=3kohms, n1=1 and n2=3 are obtained and the slope of the input/output characteristic is changed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電子回路装置に係シ、特に非線形入出力特性を
有する電子回路装置を線形入出力特性に補正した電子回
路装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to electronic circuit devices, and more particularly to an electronic circuit device in which an electronic circuit device having nonlinear input/output characteristics is corrected to have linear input/output characteristics.

従来例の構成とその問題点 第1図は、可変容量ダイオードを用いて選局される。た
とえばテレビジョン受像機の選局部の一部をできる限り
簡単に示したブロック構成図であるO 図中1は同調電圧VTが印加される端子、2は可変容量
ダイオードを含む非線形増幅回路部、そして3は信号表
示部であり、これは、たとえば、ブラウン管に映出され
る画像のチャンネルを示す。
Conventional configuration and problems thereof In FIG. 1, tuning is performed using a variable capacitance diode. For example, this is a block configuration diagram showing a part of the tuning section of a television receiver as simply as possible. 3 is a signal display section, which indicates, for example, a channel of an image displayed on a cathode ray tube.

第3図は第1図の端子1に与えた同調電圧VTと、信号
表示部3に出力されたチャンネル番号を示し、とりわけ
、VHF帯の選局植性を示す。図から明らかなように、
同調電圧vTに対して選局されるチャン戸 ・番号は非
線形で る。このことは、たとえば、:ユ調電圧■Tを
自動的に掃引して、所望の選局チャンネルを得る、いわ
ゆる、自動チューニング方式においては1次に述べる不
都合が生じる。即ち、掃引時間に対して不定間隔で画像
が映出される不自然さがあること。さらに1画像状態を
目で確認して、所望のチャンネルに固定する操作を行う
には、所定以」二の時間を要するが、非線形な入出力特
性の場合には、その傾きが最も太きいところに合わせな
ければならない。したがって、傾きが小さいところでは
、むだな時間を費すことになって、全体として掃引時間
が長くなるという不都合が存在する。
FIG. 3 shows the tuning voltage VT applied to the terminal 1 of FIG. 1 and the channel number output to the signal display section 3, and particularly shows the tuning selectivity of the VHF band. As is clear from the figure,
The channel number selected with respect to the tuning voltage vT is non-linear. For example, in the so-called automatic tuning method in which the desired selected channel is obtained by automatically sweeping the tuning voltage (1)T, the following disadvantage arises. That is, there is an unnaturalness in that images are displayed at irregular intervals with respect to the sweep time. Furthermore, it takes a certain amount of time to visually check the state of one image and fix it to the desired channel, but in the case of non-linear input/output characteristics, the slope is the steepest. must match. Therefore, where the slope is small, there is a problem that time is wasted and the overall sweep time becomes longer.

発明の目的 本発明は上記の不都合を排除するためになされたもので
あって、非線形入出力特性をほぼ線形になるように補正
した電子回路装置を提供するものである。
OBJECTS OF THE INVENTION The present invention has been made to eliminate the above-mentioned disadvantages, and provides an electronic circuit device in which nonlinear input/output characteristics are corrected to become approximately linear.

発明の構成 本発明は、非線形入出力特性を有する電気的素子、増幅
回路装置もしくは信号表示装置又はこれらの組合せで構
成した回路装置部に、前記非線形入出力特性をほぼ線形
入出力特性に補正する補正回路装置を具えた電子回路装
置であって、これによれば、入力と出力とほぼ線形にな
されるものとなる。
Composition of the Invention The present invention corrects the nonlinear input/output characteristics to approximately linear input/output characteristics in a circuit device section configured with an electrical element having nonlinear input/output characteristics, an amplifier circuit device, a signal display device, or a combination thereof. The present invention is an electronic circuit device including a correction circuit device, which allows input and output to be substantially linear.

実施例の説明 第2図は本発明にがかる一実施例プロ、り図を示す。第
1図の従来例とは補正回路部5を付加したことが相違す
る。この補正回路部5は、第3図の実線に示した非線形
入出力特性をほぼ線形に補正する機能を有する。
DESCRIPTION OF EMBODIMENTS FIG. 2 shows a diagram of an embodiment according to the present invention. The difference from the conventional example shown in FIG. 1 is that a correction circuit section 5 is added. This correction circuit section 5 has a function of substantially linearly correcting the nonlinear input/output characteristics shown by the solid line in FIG.

第4図は、第3図に示した非線形入出力特性毛はぼ線形
にするために設定された補正回路部5の入出力特注を示
す。即ち、入力端子4に印加した入力電圧■IN と端
子1に出力された同調電圧■Tとの関係を示す。
FIG. 4 shows a custom-made input/output of the correction circuit section 5, which is set to make the nonlinear input/output characteristic shown in FIG. 3 vague. That is, the relationship between the input voltage ■IN applied to the input terminal 4 and the tuning voltage ■T outputted to the terminal 1 is shown.

第5図は入力端子4に加えた入力電圧■工N と信号表
示部3に映出された画像のチャンネル番号との関係を示
す。
FIG. 5 shows the relationship between the input voltage N applied to the input terminal 4 and the channel number of the image displayed on the signal display section 3.

以下、第2図〜第5図を参照して、本発明の詳細な説明
する。
Hereinafter, the present invention will be described in detail with reference to FIGS. 2 to 5.

第2図において、入力端子4に印加した入力電圧■IN
の掃引時間tと信号表示部3に出力されるチャンネル番
号CHとの関係ΔCH/Δtは次式%式% ) (1) ここで、Δ■IN/Δt は、掃引時間tの変化に対し
てのチャンネル番号CHの変化計を示す。また、ΔCH
/Δ■T は、端子1より信号表示部3寸での入出力特
性の傾きを示す。さらに、Δ■T/Δv工Nは、補正回
路部6の入出力特性の傾きを示す。
In Fig. 2, the input voltage ■IN applied to the input terminal 4
The relationship ΔCH/Δt between the sweep time t of The change meter of channel number CH is shown. Also, ΔCH
/Δ■T indicates the slope of the input/output characteristic at 3 inches from the terminal 1 to the signal display section. Further, Δ■T/ΔvtechN indicates the slope of the input/output characteristics of the correction circuit section 6.

今、掃引時間tの変化に対してのチャンネル番号が線形
の関係にあるためには、前記(1)式のΔCH/Δt 
が一定になるように設定すればよい。
Now, in order for the channel number to have a linear relationship with the change in sweep time t, ΔCH/Δt in the equation (1) above is required.
may be set so that it is constant.

しだがって今、Δ■工N/Δt を一定とすれば、(Δ
■、/Δv工N)・(ΔCH/ΔvT)ニ一定になるよ
うに設定すればよいことが明らかであろう。
Therefore, now, if Δ■workN/Δt is constant, (Δ
It is clear that it is only necessary to set ①, /ΔvN)·(ΔCH/ΔvT) to be constant.

次に、第3図より、ΔCH/ΔvT を求めてみる。Next, from FIG. 3, try to find ΔCH/ΔvT.

第3図に例示したHチャンネルの入出力特性を、その傾
きをm11m2  に示す2つの直線で近似し、Lチャ
ンネルの入出力特性の傾きをm3に示す直線で近似して
みると、ml−1(CH/V)2m2−%(CH2N)
9m3−%(CH/■)となる。
If we approximate the input/output characteristics of the H channel illustrated in Figure 3 with two straight lines whose slopes are shown as m11m2, and the slope of the input/output characteristics of the L channel with a straight line shown as m3, we get ml-1. (CH/V)2m2-%(CH2N)
9m3-% (CH/■).

さて、第3図に例示した非線形入出力特性をほぼ直線に
補正するだめの補正回路部5に要求される傾きを、上記
m15m22m3に対してそれぞれn 1. n 2 
、 n sとし、たとえば−例としてnl−1げ設定す
るならば、上記(1)式を満足するために、n2−3.
n3=2となる。即ち、補正回路部5のノ出力特性の傾
きが、それぞれ−n1=1 、n2=3゜n3−2をも
った補正回路部5を配置すればよい。
Now, the slopes required of the correction circuit section 5 to correct the nonlinear input/output characteristics illustrated in FIG. n 2
, n s and, for example, if nl-1 is set, n2-3.
n3=2. That is, it is sufficient to arrange the correction circuit section 5 in which the slope of the output characteristic of the correction circuit section 5 is -n1=1 and n2=3°n3-2, respectively.

第5図は、補正回路部を付加し、さらに第4図←)に示
したHチャンネルを補正する特性と、同(ホ)に示した
Lチャンネルを補正する特性とを切換えるようにして、
1つの直線に変換した特性を示す。
In FIG. 5, a correction circuit section is added, and the characteristics for correcting the H channel shown in FIG. 4 (←) and the characteristics for correcting the L channel shown in FIG.
It shows the characteristics converted into one straight line.

ここで、1つの直線に変換するためには、たとえば、L
チャンネルのチャンネル番号3と、Hチャンネルのチャ
ンネル番号4との境界の入力電圧”IN  を検出し、
たとえば、”IN=6.5V以下の時にLチャンネルを
、■IN=5.5■以上の時にはHチャンネルをそれぞ
れ選択するよう設定ずればよい。
Here, in order to convert to one straight line, for example, L
Detects the input voltage "IN" at the boundary between channel number 3 of the channel and channel number 4 of the H channel,
For example, the L channel may be selected when IN=6.5V or less, and the H channel may be selected when IN=5.5V or more.

第6図は、補正回路部5の具体的な一実施例回路図を示
す。
FIG. 6 shows a circuit diagram of a specific embodiment of the correction circuit unit 5. In FIG.

図中7は電源端子、8と9は基準電圧媒子、11と12
は直流電圧印加端子、13と14は電流源用トランジス
タ、15,16,21,22,23゜24はエミッタ抵
抗、17〜20は差動増幅器用トランジスタ、25はダ
イオード、26は出力トランジスタ、そして27はコレ
クタ負荷抵抗である。ここで、第2図と同じ個所VCは
同一番−シフ−を付−I) しプこ。
In the figure, 7 is a power supply terminal, 8 and 9 are reference voltage mediums, 11 and 12
are DC voltage application terminals, 13 and 14 are current source transistors, 15, 16, 21, 22, 23° 24 are emitter resistors, 17 to 20 are differential amplifier transistors, 25 is a diode, 26 is an output transistor, and 27 is a collector load resistance. Here, the same parts of VC as in Fig. 2 are marked with the same number -I).

次に動作を説明する。まず、抵抗21と22の抵抗値は
共に等しくその値をR1、抵抗23と24の抵抗値は共
に等しくその値をR2、さらに抵抗27の抵抗値R3と
する。さらに、基準電圧端子8゜9(Dそn−tft’
7)’!圧’i:”REFl 、”REF2とし、とれ
らの関係はたとえば、”REFl<”REF2に選はれ
ているとする。
Next, the operation will be explained. First, the resistance values of the resistors 21 and 22 are both equal and their value is R1, the resistance values of the resistors 23 and 24 are both equal and their value is R2, and the resistance value of the resistor 27 is R3. Furthermore, the reference voltage terminal 8°9 (Dson-tft'
7)'! It is assumed that the pressures 'i: "REF1" and "REF2" are selected, and the relationship between them is, for example, "REF1<"REF2.

今、入力端子4に印加した入力電圧■IN が、基準電
圧源vREF1とほぼ等しい時の電圧利得n1は、 n1′5R3/2・R1−・・・(2)として表わされ
る。
When the input voltage IN applied to the input terminal 4 is almost equal to the reference voltage source vREF1, the voltage gain n1 is expressed as n1'5R3/2.R1- (2).

寸だ、入力電圧vIN をさらに大きくして、基準電圧
源vREF2とほぼ等しくなった時−の電圧利得n2は
・ R2−R3/2−R1+R3/2−R2、、、、、、、
、、(s)となる。
When the input voltage vIN is further increased and becomes almost equal to the reference voltage source vREF2, the voltage gain n2 is ・R2-R3/2-R1+R3/2-R2, , , , ,
,,(s).

したがって、たとえば、R=1.rsKQ 、 R2=
o 、 −rrsKi) 、 R3’:3にΩに設定す
ると−n1=1゜n2=3が得られる。即ち、第3図に
示した非線形をほぼ線形な入出力特性に補正するように
して、第4図に)に示した特性に選ばれたことが理解で
きよう。また、第4図(ホ)に示した特性は第3図のL
チャンネルを補正するために、傾きR3−2に設定され
た特性を示す。
Therefore, for example, R=1. rsKQ, R2=
o, -rrsKi), R3': If 3 is set to Ω, -n1=1°n2=3 is obtained. That is, it can be understood that the characteristics shown in FIG. 4) were selected by correcting the nonlinearity shown in FIG. 3 to almost linear input/output characteristics. Also, the characteristics shown in Figure 4 (E) are the same as those shown in Figure 3.
In order to correct the channel, a characteristic set to slope R3-2 is shown.

次に第4図(ロ)において、LチャンネルとLチヤンネ
ルとの切換点での入力電圧■工N1の値は、前記■RE
F1と抵抗21.22の抵抗値R1およびトランジスタ
13のコレクタ電流Io1 によって定められ、 ”lN1=”REFl−101・R1”   個として
表わすことができる。寸だ、傾きnlとR2との交点の
入力電圧■IN2は、トランジスタ14のコレクタ電流
をIO2とすると、 ■lN2zVREF2−工02・R2(5)として設定
することが可能である。ここて−■IN2の値は、第3
図(イ)および(ロ)に近似した直線との交点、即ち■
T−11■になる点を設定すればよい。
Next, in FIG. 4 (b), the value of the input voltage N1 at the switching point between the L channel and the L channel is
It is determined by F1, the resistance value R1 of the resistor 21.22, and the collector current Io1 of the transistor 13, and can be expressed as "lN1="REFl-101・R1".It is the input of the intersection of the slope nl and R2. The voltage ■IN2 can be set as ■IN2zVREF2−02·R2 (5), where the collector current of the transistor 14 is IO2.Here, the value of −■IN2 is the third
The intersection with the straight line approximated in figures (a) and (b), that is, ■
What is necessary is to set the point at which T-11■.

なお、本発明の一実施例においては、Lチヤンネルを2
つの直線で近似して、2段の差動増幅器を配置したが、
近似した直線の数に応じた段数の増幅器を設定すればよ
いことは詳述するまでもなく明らかであろう。
Note that in one embodiment of the present invention, the L channel is
I arranged a two-stage differential amplifier by approximating it with two straight lines, but
It is obvious that the number of stages of amplifiers should be set in accordance with the number of approximated straight lines, without the need for detailed explanation.

発明の効果 以上の実施例を用いて説明したように、本発明によれば
、非線形な入出力特性はほぼ線形に補正されるために、
たとえば、入力電圧を自動的に掃引して出力信号を得る
回路装置等においては、出力信号が不定間隔で出力され
るという不自然性は解消されるものとなる。さらに本発
明によれば、電子回路装置等の操作に好適な上記掃引時
間を有効に設定することが可能となる。
Effects of the Invention As explained using the above embodiments, according to the present invention, nonlinear input/output characteristics are corrected almost linearly.
For example, in a circuit device or the like that automatically sweeps an input voltage to obtain an output signal, the unnaturalness that the output signal is output at irregular intervals can be eliminated. Further, according to the present invention, it is possible to effectively set the above-mentioned sweep time suitable for operating an electronic circuit device or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、電子回路装置の従来の選局部を簡単に示した
図、第2図は本発明の一実施例を示すプロJり図、第3
図は選局特性を示す図、第4図は本発明に係る補正回路
部の特性図、第6図は本発明の電子回路装置の入出力特
性を示す図、第6図は補正回路部の一具体的回路図を示
す。 1・・・・端子、2 ・非線形増幅回路部、3信号表示
部、4  入力端子、5・−一補正回路部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 :″−J2図 第3図 4  6B  IO!2 14  /l  Ill  
20V7CV)IJ真問贋ζ刀三 第4図 VrN(V) 入力し 第5図 2  4  4   B   IQ   /2  /4
Vm(V) 入力を圧
FIG. 1 is a diagram simply showing a conventional tuning section of an electronic circuit device, FIG. 2 is a professional diagram showing an embodiment of the present invention, and FIG.
4 is a diagram showing the characteristics of the correction circuit section according to the present invention. FIG. 6 is a diagram showing the input/output characteristics of the electronic circuit device of the present invention. A specific circuit diagram is shown. 1: terminal, 2: nonlinear amplifier circuit section, 3: signal display section, 4: input terminal, 5: -1 correction circuit section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure: ″-J2 Figure 3 Figure 4 6B IO!2 14 /l Ill
20V7CV) IJ True Question False ζ Tosan Figure 4 VrN (V) Input Figure 5 2 4 4 B IQ /2 /4
Vm (V) Pressure input

Claims (1)

【特許請求の範囲】[Claims] 非線形入出力特性を有する電気的素子もしくは増幅回路
装置もしくは信号表示装置又はこれらの組合せで構成し
た回路装置部に、前記非線形入出力特性をほぼ線形入出
力特性に補正する補正回路装置を具えた電子回路装置。
An electronic device comprising a correction circuit device for correcting the nonlinear input/output characteristics to approximately linear input/output characteristics in a circuit device section constituted by an electrical element having nonlinear input/output characteristics, an amplifier circuit device, a signal display device, or a combination thereof. circuit device.
JP9432183A 1983-05-27 1983-05-27 Electronic circuit device Pending JPS59219006A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9432183A JPS59219006A (en) 1983-05-27 1983-05-27 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9432183A JPS59219006A (en) 1983-05-27 1983-05-27 Electronic circuit device

Publications (1)

Publication Number Publication Date
JPS59219006A true JPS59219006A (en) 1984-12-10

Family

ID=14107012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9432183A Pending JPS59219006A (en) 1983-05-27 1983-05-27 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPS59219006A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5514798A (en) * 1978-07-13 1980-02-01 Licentia Gmbh Circuit device for genetating controlled dc voltage depending on ac voltage
JPS5666909A (en) * 1979-11-02 1981-06-05 Nec Corp Predistorter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5514798A (en) * 1978-07-13 1980-02-01 Licentia Gmbh Circuit device for genetating controlled dc voltage depending on ac voltage
JPS5666909A (en) * 1979-11-02 1981-06-05 Nec Corp Predistorter

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