JPS59211342A - Fault supervising circuit - Google Patents

Abstract

PURPOSE:To measure the duration time of plural fault information by one counter circuit by applying time division and multiplex at each unit to the plural fault information then multiplexing the resulted information in time series, and sampling the duration time of said information having an fault at each specific period. CONSTITUTION:Pieces of fault information a1-al detected by units U1-Un are multiplexed by a multiplexing circuit 5 in each unit. The wired-OR constitution is adopted by using a tri-state buffer 6 in order to apply multiplication further. A supervising section SV consists of a counter circuit 7, a memory circuit 9 and a flip-flop circuit 8 or the like. The counter circuit 7 inputs duration time information read by a memory circuit 9 based on input fault information 6-1, stores this output information at a flip-flop circuit 8 and inputs it to the memory circuit 9. Then, the duration time at each fault type is counted by one counter circuit 7 by using the counter circuit in terms of time division.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault monitoring circuit that collects a plurality of pieces of fault information and monitors their fault states.

In a conventional fault monitoring circuit, when realizing a monitoring circuit that stores fault information when a fault continues for a certain period of time or more, the configuration shown in FIG. 1 is used.

In Figure 1, each unit) U 1 ---- U n
The fault information a l ----a j detected by the fault detection circuit l provided therein is independently transmitted to the monitoring section Sv. The monitoring unit Sv measures the duration of the fault information, and stores the fault in the storage circuit 4 when it continues for a certain amount of time. In this case, as the failure type a---a4 and the number of units n become large, it becomes impossible to calculate the total failure duration time for each individually by 611. Therefore, various failure information is input to the OR circuit 2, and the The output was measured by one time counting circuit 3.

In this case, since the duration time for each fault type cannot be determined, all of the woodcutter fault states are written in the memory circuit 4 at once when storing them as continuous faults.

In such a configuration, there is a risk that a fault that occurs accidentally at the moment it is stored as a continuous fault may also be stored as a continuous fault, or that it may be mistaken as a continuous fault due to the overlap of multiple faults.Furthermore, there is a risk that the number of units Also, as the number of failure types increases, the number of failure information transmission lines cannot be ignored.

SUMMARY OF THE INVENTION An object of the present invention is to provide a fault monitoring circuit that can avoid the above-mentioned drawbacks by multiplexing fault information output from each unit and performing fault monitoring at the multiplexed level in a monitoring section.

The fault monitoring circuit of the present invention includes means for time-division multiplexing a plurality of pieces of fault information for each unit, means for further multiplexing the output in time series, and specifying the duration time of faulty information of the fault information. A counting circuit for measuring by sampling every cycle, a holding circuit for temporarily holding the output thereof, a storage circuit for storing the output, a detection circuit for monitoring the output of the holding circuit, and a storage circuit for the fault information. , and a pulse generating circuit, and is characterized in that one counting circuit measures the duration of a plurality of pieces of fault information.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows its operation timing diagram.

In Figure 2, each unit) U 1 ---- U n
The fault information ab--al detected in each unit is multiplexed by a multiplexing circuit 5 in each unit. In order to further multiplex this unit-by-unit multiplexed information, a 3-state buffer 6 is used and a C wired-OR configuration is used. At this time, the control signal 10- given to the 3-state buffer is in a form that outputs the fault information of the unit within a desired time slot. For example, the control signal 10- given to the unit Uk is as shown in FIG. Become.

On the other hand, the monitoring unit Sv uses multiple processing technology to monitor this multiplexing failure information at the same multiplexing level.

This is counting circuit 7. It is composed of a memory circuit 9, a flip-flop circuit 8, etc., and as a control signal for the memory circuit 9, as shown in FIG. It is generated by the pulse generation circuit 10.

- At this time, the counting circuit 7 calculates the duration information (DO output) read out by the memory circuit 9 based on the input failure information 6-1.
is input, and determines whether to further count up or reset it. This output information (OUT) is held in the flip-flop circuit 8, and stored as new duration information in the memory circuit 9 (DI).

In this way, by using the counting circuit 7 in a time-sharing manner, it becomes possible to count the duration time for each fault type using one counting circuit 7.

On the other hand, continuous fault information can be stored in the memory circuit 12 by monitoring the output of the counting circuit 7 with the detection circuit 11. For example, in FIG. 3, failure information a2 of unit Uk
indicates "Failure present -" and if this continues for a certain period of time, the output of the detection circuit 11 (Fig. 3 11-1.) indicates that
The failure information a2 is written to address 2 of the memory circuit 12 in time slot T.

As is clear from the above description, according to the present invention, it is possible to count the duration for each fault type, and the drawbacks of the conventional method described above can be completely avoided. Furthermore, the number of interface lines between each unit and the monitoring section can be suppressed to the minimum required number as the number of units and types of failures increases.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a conventional fault monitoring circuit.
The figure is a configuration diagram showing an embodiment according to the present invention, and FIG. 3 is a timing diagram showing its operation. 1...Fault detection circuit, 2...Par°°OR circuit, 3...Time counting circuit, 4...Memory circuit, 5...Multiple circuit, 6...3-state buffer, 7...counting circuit, 8...
・Flip-flop circuit, 9.12...Memory circuit, 10...Pulse generation circuit, 11...
...Detection circuit.

Claims (1)

[Claims] A means for time-division multiplexing a plurality of pieces of fault information for each unit, a means for further multiplexing the output in time series, and a duration time of the fault information of the fault information being measured by sampling at specific cycles. A counting circuit, a holding circuit that temporarily holds the output, and a memory circuit that stores the output.
comprising a detection circuit that monitors the output of the holding circuit, a storage circuit for the failure information, and a pulse generation circuit,
Measuring the duration of multiple failure information with one counting circuit! Fault monitoring circuit with mold.