JPS5921045A - Forming method for bump for connection - Google Patents

Forming method for bump for connection

Info

Publication number
JPS5921045A
JPS5921045A JP57131402A JP13140282A JPS5921045A JP S5921045 A JPS5921045 A JP S5921045A JP 57131402 A JP57131402 A JP 57131402A JP 13140282 A JP13140282 A JP 13140282A JP S5921045 A JPS5921045 A JP S5921045A
Authority
JP
Japan
Prior art keywords
resist film
bump
substrate
bumps
type resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57131402A
Other languages
Japanese (ja)
Inventor
Shoji Nomura
昭司 野村
Shusaku Shibata
修作 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57131402A priority Critical patent/JPS5921045A/en
Publication of JPS5921045A publication Critical patent/JPS5921045A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]

Abstract

PURPOSE:To form the high bump easily on a substrate, on which the bump is to be disposed through a lift-off method by coating a negative type resist film with an opening with a conductor layer and dissolving and removing each resist film. CONSTITUTION:A first positive type resist film 22 is applied on the substrate 21 on which a bump is to be formed, and dried and cured, and the resist film 22 is coated with a first metallic layer 23 of an element such as aluminum. The upper surface of the metallic layer 23 is coated similarly with a second positive type resist film 24 and a second metallic layer 25 of Al. The second metallic layer 25 exposed to an opening section 27 is removed selectively through etching while using a negative type resist film 26 with the opening section 27 as a mask, and the second positive type resist film 24 exposed is exposed selectively, and dissolved and removed by a developer. The surface is coated thickly with a good- conductive metallic conductor layer 29 of indium, etc. The positive type resist films 22, 24 to which the disposing hole 28 is formed are dissolved by a resist exfoliating liquid.

Description

【発明の詳細な説明】 (+1)発明の技術分野 本発明は半導体チップ等からなる能動素子をフェースダ
ウンボンディング法によって受動回路基板上に実装する
に用いられるバンプを長身に形成し得る接続用バンブの
形成方法に関するものである。
Detailed Description of the Invention (+1) Technical Field of the Invention The present invention relates to a connection bump that can be used to mount an active element such as a semiconductor chip on a passive circuit board by a face-down bonding method and can form a long bump. This relates to a method of forming.

(b)  従来技術と問題点 一般にハイブリッドIC等の組立において、半導体チッ
プ等からなる能動素子を受動回路基板−Lに実装する一
方法として、前記半導体チップの接続端子、あるいは前
記受動回路基板の接合端部゛またはこれら双方の接続、
接合部に、比較的軟かいインジウム(In)等からなる
導電性のバンプを形成シ、かかる半導体チップのバンプ
配設部を対応する前記回路基板の接続点に重ね合わせ、
圧接することによって該半導体チップを回路基板上に機
械的に固定すると共に電気的な接続を行うフェースダウ
ンボンディングが知られており、同時に多蝕接点の接続
が可能であると共に回路基板に対する半導体チップの実
装密度を上げることができる利点を有している。ところ
で上述したフェースダウンボンディングに用いられるバ
ンプは、従来例えば第1図に示すようにバンプを形成す
べき基板1  1−V7f d 散θ)’7  ”k 
 +−1/ +7 7 1−  M鋤 0  ’t−蛤
自ul    ”Inいで該ポジ形フオl−レジスト膜
2上にさらにネガ形のフォトレジスト膜3を塗着しだ後
、前記基板1のバンプを形成すべき領域上のネガ形フォ
トレジスト膜3およびポジ形フォトレジスト膜2を順に
所定パターンにパターニングして第2図に示すように開
口部4を設ける。そして前記開口部4を有するネガ形フ
ォトレジスト膜8上の全面にインジウム(In)等から
なる導電性のよい金属導電体層5を例えば蒸着法によっ
て被着し、しかる後前記各しジヌト膜2,8をレジスト
剥離液によって溶解除去することによって第3図に示す
如くバンプ6を形成している。ところが上記の如きリフ
トオフ法によるバンプの形成方法にあっては1度に複数
個のバンプを形成できる利点を有する反面、形成された
バンプ6の高さが、前記基板」二にパターニングされた
レジスト膜の厚さによって制限される。従って上述した
ようにバンプを形成すべき基板1上にポジ形のフォトレ
ジスト膜2とネガ形のフォトレジヌトを2層に積層する
方法によってバンプ6を高く形成しているが、実際には
5〜6μm程度の高さにしか形成されず、バンプ接続を
好適になし得る少なくとも10μm以上の高さを有する
バンプを形成することが容易でない欠点があった。
(b) Prior Art and Problems In general, in the assembly of hybrid ICs, etc., one method for mounting active elements such as semiconductor chips on a passive circuit board-L is to use connection terminals of the semiconductor chip or bonding of the passive circuit board. Connection of the ends or both of these,
Forming conductive bumps made of relatively soft indium (In) or the like at the bonding portions, overlapping the bump placement portions of the semiconductor chip onto the corresponding connection points of the circuit board,
Face-down bonding is known, in which the semiconductor chip is mechanically fixed on the circuit board by pressure bonding and electrically connected, and at the same time, it is possible to connect multi-corrosion contacts, and it is also possible to connect the semiconductor chip to the circuit board. It has the advantage of increasing packaging density. By the way, the bumps used in the above-mentioned face-down bonding have conventionally been formed on a substrate 1 on which the bumps are to be formed, for example, as shown in FIG.
+-1/ +7 7 1- After coating the negative photoresist film 3 on the positive photoresist film 2 with In, the substrate 1 is coated with a negative photoresist film 3. The negative photoresist film 3 and the positive photoresist film 2 on the area where bumps are to be formed are sequentially patterned into a predetermined pattern to form openings 4 as shown in FIG. A highly conductive metal layer 5 made of indium (In) or the like is deposited on the entire surface of the shaped photoresist film 8 by, for example, vapor deposition, and then each of the dinut films 2 and 8 is dissolved with a resist stripping solution. By removing the bumps 6, as shown in FIG. 3, the bumps 6 are formed as shown in FIG. The height of the bumps 6 is limited by the thickness of the resist film patterned on the substrate. Therefore, as described above, the bumps 6 are formed high by laminating two layers of a positive photoresist film 2 and a negative photoresist film on the substrate 1 on which the bumps are to be formed, but in reality, the height is 5 to 6 μm. However, it is difficult to form bumps having a height of at least 10 μm or more, which would allow suitable bump connection.

(C)発明の目的 本発明は上記従来の問題点を克服し、リフトオフ法によ
ってバンプを形成すべき基板上に、バンプ接続を好適に
なし得る従来よりも高いバンプを容易に形成することが
できる新規な接続用バンプの形成方法を提供することを
目的とするものである。
(C) Object of the Invention The present invention overcomes the above-mentioned conventional problems, and can easily form higher bumps than conventional ones that can suitably connect bumps on a substrate on which bumps are to be formed by a lift-off method. The object of the present invention is to provide a novel method for forming connection bumps.

(d、)  発明の構成 そして上記目的は本発明によれば、バンプを形成すべき
基板上にポジ形レジスト膜と金属層とを交互に多層被着
し、最上層となる前記金属層上にネガ形レジストを塗着
した後、該ネガ形しジヌト膜の所定領域を開口すべく、
パターニングし、こ     □のレジスト膜をマスク
にして前記開口に露出する’fmE4Ji1.Mh L
 Ug 5)Ye v =) y−) J[I!el頃
*、 肝。
(d.) Structure of the Invention According to the present invention, positive resist films and metal layers are alternately deposited in multiple layers on a substrate on which bumps are to be formed, and the uppermost metal layer is coated with a positive resist film and a metal layer. After applying the negative resist, in order to open a predetermined area of the negative resist film,
'fmE4Ji1. Mh L
Ug 5) Ye v =) y-) J[I! Around el*, liver.

的に除去し、しかる後前記開口を有するネガ形し   
  □シスト膜上に導電体層を被着し、次いで前記各レ
ジスト膜を溶解除去して前記基板上に高い接続用バンプ
を形成することを特徴とする接続用バンプの形成方法を
提供することによって達成される。
and then remove the negative mold with said aperture.
□By providing a method for forming a connection bump, which comprises depositing a conductor layer on a cyst film, and then dissolving and removing each of the resist films to form a high connection bump on the substrate. achieved.

(e)  発明の実施例 以下図面を用いて本発明の好ましい実施例について詳細
に説明する。
(e) Embodiments of the invention Preferred embodiments of the invention will be described in detail below with reference to the drawings.

第4図乃至第7図は本発明に係る接続用バンプの形成方
法の一実施例を工程順に示す要部断面図である。まず第
4図に示すようにバンプを形成すべき基板21上に第1
のポジ形レジスト膜22塗布し、乾燥硬化後その上に例
えばアルミニウム(Ae)からなる第1の金属層23を
蒸着法等によυ被着する。さらにその上面に同様にして
第2のポジ形レジメト膜24およびAlからなる第2の
金属層25を被着する。次いで該第2の金属層25の表
面にネガ形レジスト膜26を被覆した後、第5図に示す
ように前記基板21のバンプを形成すべき領域上のネガ
形レジスト膜26を所定バターて該開口部27を有する
ネガ形レジスト膜26をマスクにして前記開口部27に
露出した第2の金     □属層25を選択的にエツ
チング除去し、次に露出した第2のポジ形しジヌト膜2
4を選択的に露光し、現像液によって溶解除去する。以
下同様にして前記開口部27に、順に露出する第1の金
属層28および第1のポジ形しジヌト膜22を選択的に
除去してバンプ配設穴28を設けた後、該配設穴28を
含む前記ネガ形しジヌト膜26上の全面に蒸着法によっ
て第6図に示すように例えばインジウム(In)等から
なる軟かい導電性のよい金属導電体層29を厚く被着す
る。次いで前記配設穴28を形成した例えば第1および
第2のポジ形し     1シスト膜22.24を、該
レジスト剥離液によって溶解することによシ前記第1お
よび第2の金属層23.25も共に除去する(リフトオ
フ工程)     □′:ことによって第7図に示すよ
うに前記基板21上の所定位置に所望の高さを有するバ
ンプ80を容易に形成することができる。
FIGS. 4 to 7 are sectional views of main parts showing an embodiment of the method for forming a connection bump according to the present invention in the order of steps. First, as shown in FIG.
A positive resist film 22 is applied, and after drying and hardening, a first metal layer 23 made of, for example, aluminum (Ae) is deposited thereon by vapor deposition or the like. Furthermore, a second positive regime film 24 and a second metal layer 25 made of Al are deposited on the upper surface in the same manner. Next, after coating the surface of the second metal layer 25 with a negative resist film 26, as shown in FIG. Using the negative resist film 26 having the opening 27 as a mask, the second metal layer 25 exposed in the opening 27 is selectively removed by etching, and then the exposed second positive resist film 2 is removed.
4 is selectively exposed to light and dissolved and removed using a developer. Thereafter, in the same manner, after selectively removing the first metal layer 28 and the first positive dinut film 22 exposed in the opening 27 in order to provide a bump placement hole 28, the bump placement hole 28 is formed in the opening 27. As shown in FIG. 6, a soft metal conductor layer 29 made of, for example, indium (In) or the like is thickly deposited on the entire surface of the negative-shaped dinut film 26 including the film 28, as shown in FIG. Next, the first and second metal layers 23, 25 are removed by dissolving, for example, the first and second positive-type cyst films 22, 24 in which the arrangement holes 28 are formed, with the resist stripping solution. (Lift-off step) □': As a result, a bump 80 having a desired height can be easily formed at a predetermined position on the substrate 21 as shown in FIG.

めに、Jξフシ形・ジス1叫IQと金属I蕾とを2層づ
つ積層し/こ場合の例について説明し/こが、本角明ば
これに限定きれるものではなく、要求される7<ンフ゛
の高さに応じてポジ形しジスト膜と金属層の積層数を変
化させて実施できるととは元うまでもない。
In order to achieve this, we will laminate two layers each of JξFushi-shaped JIS 1-layer IQ and metal I-bud./We will explain an example of this case/However, this is not limited to this, but the required <It goes without saying that it is possible to carry out the method by changing the number of laminated layers of a positive resist film and metal layer depending on the height of the amplifier.

(f)  発明の効果 以上の説明から明らかなように本発明に係る接続用バン
プの形成力法によれば、バンプを配設すべき基板にに、
リフトオフ法によって所望とする従来よりも高いバンプ
を容易に形成することができる利点を有し、フェースダ
ウンボンディング法によって能動素子を受動回路基板」
−に実装するに用いられる各種接続用バンプの形成工程
に適用して(メめて有利である。
(f) Effects of the invention As is clear from the above explanation, according to the connection bump forming force method according to the present invention, on the substrate on which the bumps are to be arranged,
The lift-off method has the advantage of easily forming bumps that are higher than conventional ones, and the face-down bonding method allows active elements to be bonded to passive circuit boards.
- It is very advantageous to apply it to the formation process of various connection bumps used for mounting on devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は従来の接続用バンプの形成方法を工
程順に説明する要部断面図、第4図乃至第7図は本発明
に係る接続用バンプの形成方法の一実施例を工程)1@
に示す要部断面図である。 図面において21は基板、22.24は第1おおよび第
2の金属層、26はネガ形しジスト膜、27は聞1】部
、28はバンプ配設穴、29B、、1、金属導電体層、
80は接続用バンブを示す。 第1図 第2図 第3図 第4図 第5図 第6図 フq 第7図
1 to 3 are cross-sectional views of main parts explaining a conventional connection bump forming method step by step, and FIGS. 4 to 7 show an example of the connection bump forming method according to the present invention. )1@
FIG. In the drawings, 21 is a substrate, 22, 24 are first and second metal layers, 26 is a negative resist film, 27 is a 1] part, 28 is a bump arrangement hole, 29B, 1, a metal conductor layer,
80 indicates a connecting bump. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】 バンプを形成ずべき基板トにポジ形しジスト膜と金属層
とを交互に多層被着し、最−に層となる前に己金属層」
二にネガ形レジストを塗着し/こ後、該ネガ形1.・シ
スト)漢の所定領域を開口すべくバターニングし2、こ
のレジスト膜をマスクにして前記間「1に露出する前記
金属層およびポジ形しジスト膜を順次、選択的に除去し
、1〜かる後、前記開口を有するネガ形レジスト膜上に
導電体層を被着し、次いで前記各レジスト膜を溶解除去
して、前記基板上に長身の接続用バンプを形成すること
を特徴とする接続用バンブの形成方法。 糺
[Claims] "A positive resist film and a metal layer are alternately deposited in multiple layers on a substrate on which bumps are to be formed, and a self-metal layer is applied before forming the final layer."
Apply a negative resist to 1. After that, apply a negative resist to 1. - Buttering a predetermined area of the cyst (cyst) to open it 2, using this resist film as a mask, selectively remove the metal layer and the positive resist film exposed in 1 during the above steps, 1 to 2. After that, a conductor layer is deposited on the negative resist film having the opening, and then each of the resist films is dissolved and removed to form a tall connection bump on the substrate. Method for forming bumps for use.
JP57131402A 1982-07-27 1982-07-27 Forming method for bump for connection Pending JPS5921045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57131402A JPS5921045A (en) 1982-07-27 1982-07-27 Forming method for bump for connection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57131402A JPS5921045A (en) 1982-07-27 1982-07-27 Forming method for bump for connection

Publications (1)

Publication Number Publication Date
JPS5921045A true JPS5921045A (en) 1984-02-02

Family

ID=15057132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57131402A Pending JPS5921045A (en) 1982-07-27 1982-07-27 Forming method for bump for connection

Country Status (1)

Country Link
JP (1) JPS5921045A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536677A (en) * 1994-12-01 1996-07-16 Motorola, Inc. Method of forming conductive bumps on a semiconductor device using a double mask structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5536677A (en) * 1994-12-01 1996-07-16 Motorola, Inc. Method of forming conductive bumps on a semiconductor device using a double mask structure

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