JPS59198752A - Mos type dynamic memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the capacity for accumulating charges without a group structure and thus improve the integration degree by a method wherein a poly Si layer at the same potential as a semiconductor layer is arranged on the latter layer, and the other poly Si layer is arranged so as to be sandwiched between the poly Si layer and the semiconductor layer via insulation film. CONSTITUTION:The surface of a P type Si substrate 5 is thinly oxidized, and further a nitride film is formed, thus performing LOCOS oxidation, and thereafter ion implantation is performed with a photo resist film as a mask. After forming the first insulation film composed of an oxide film 32 and a nitride film 33, a poly Si layer 34 as the first poly Si layer is formed and then treated with phosphorus. After forming the poly Si layer over the entire surface as shown by a broken line and puttig it through the phosphorus treatment, only this layer is selectively etched by RIE. The dimension (c) of a side wall 39 at the part covering an N<-> diffused layer 9 can be controlled by the thickness of the first poly Si layer. Next, the whole is oxidized by wetting. As a result, a thick oxide film 40 is formed on the second poly Si layer 37, and a thin oxide film 41 on the gate surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an MO8 type dynamic memory in which a semiconductor layer of a conductivity type opposite to that of a semiconductor substrate is provided under a memory insulating film, and a method for manufacturing the same.

[Background of the invention]

MO8 type dynamic memory (D/
Most of RAM) has one capacity and MOS) transistor (
It has a structure called 1-Tcell consisting of one MOS FET).

FIG. 1 shows an example of the configuration of such a memory.

In the figure, S is the source of the MOS transistor 1, D is the drain, and 2 is the capacitance, and the range surrounded by the chain line constitutes one bit. 3 indicates a word line driver, 4 indicates a bit line driver and a sense amplifier (U, S,
Pat, 3,387,286. Jne 4, 1968
).

Such a memory cell is configured, for example, as shown in FIG. 2(A), and has several circuits as shown in FIG. 2(B). That is, the power supply voltage Vcc is constantly applied to the memory section formed in the region surrounded by the element isolation insulating film 6 of the P-type silicon substrate 5, and this
) H level signal N tn (vCC) and L level signal “o” applied to data line T through a transistor
(ov) is applied to the depletion layer or oxide film portion under the memory oxide film 8. G indicates the gate of a MOS transistor. In the figure, the depletion layer during "0" writing shown as a is expanded as shown by b during "1" writing, so the capacitance value at that time is compared to the capacitance Cox during "0" level writing. Usually, the charge amount C0X(V
cc -Vth) is exchanged between the data line and the memory cell to function as a memory. In addition,
In Figure 2, COX is the oxide film capacitance, Cd is the depletion layer capacitance, and the capacitance seen from the vin input side is C-Cox + Cd.
: Represented by Cox. Incidentally, i is an oxide film charging current necessary to shift from level to level level at the time of "0" level writing, and is a so-called "0" level write current. vth indicates threshold voltage.

The principle of operation as described above does not fundamentally change even in a structure in which an ON-diffusion layer 9 of the conductivity type opposite to that of the semiconductor substrate is provided under the memory oxide film 8 of the semiconductor substrate 5 as shown in Fig. 3 (IE ED-26, pp839.1979).

In this case, a so-called "grounded plane" memory configuration can be adopted in which there is no power supply voltage for the memory cell. At this time, when the H level signal "1" is written, a sufficient amount of charge Cox (
Vin-Vth) is stored in the memory cell.

By the way, as the capacity of such memory increases from 64 bits to 256 bits and further to 1M bit,
The device dimensions of one memory unit are becoming smaller and smaller, the cell area is also becoming smaller, and the signal charge that can be taken out is becoming smaller and smaller, and problems are starting to arise in terms of noise margin against external disturbances such as alpha rays. For this reason, many improved structures have been proposed, but most of them form deep grooves or groups in the cell portion, thereby increasing the cell area and attempting to accumulate charges deep within the group. It is something.

However, in this case, it is not possible to bring the distance between cells closer than a certain limit due to difficulties in controlling the group depth, breakdown voltage deterioration at the corners of the group, and interference between groups when memory cells are brought close together. , memo IJLSI
It was not possible to sufficiently increase the degree of integration.

[Purpose of the invention]

The present invention was made in view of these circumstances, and
The object of the present invention is to provide an MO8 type dynamic memory and a method for manufacturing the same, which can enhance the charge storage capacity and increase the degree of integration without using a group structure.

[Summary of the invention]

In order to achieve such an object, the present invention provides an MO in which a semiconductor layer of an opposite conductivity type is provided on a semiconductor substrate under a memory insulating film.
In an 8-type dynamic memory, that is, a memory configuration of a grounded memory cell, a polysilicon layer having the same potential as the semiconductor layer is disposed on the semiconductor layer, and an insulating film is provided between the polysilicon layer and the semiconductor layer. Another polysilicon layer connected to the power supply line is placed between them. In addition, in order to realize such a structure, a first insulating film, a first polysilicon layer, a second insulating film, and a second polysilicon layer are formed on a semiconductor layer of opposite conductivity type formed on a semiconductor substrate. The end face of the second polysilicon layer and the semiconductor layer are connected by the sidewalls of the polysilicon layer by sequentially stacking the insulating film and polysilicon layer formed over these layers using an anisotropic etching method. It is something to do. Hereinafter, the present invention will be explained in detail using Examples.

[Embodiments of the invention]

FIG. 4 is a sectional view of an MO8 type dynamic memory showing one embodiment of the present invention, and the same or equivalent parts as in FIG. 3 are designated by the same symbols. In Europe, in Figure 4, 5
is a P-type silicon substrate or a P-WELL layer, and an element isolation insulating film 6 made of a LOCO8 film is formed thereon.
N- which forms a PN junction that becomes a capacitor in the area surrounded by
Diffusion layer 9 and MOS) transistor source-drain layers 21 and 22 are formed, and the source-drain layer 21
A polysilicon layer 24 serving as a gate is formed on 22 and 22 with an insulating film 23 interposed therebetween. Further, a passivation film 25 made of PSG is formed to cover this layer.

Here, a polysilicon layer 26 connected to the N-diffusion layer 9 at the end is formed on top of the N-diffusion layer 9, and a memory insulating film is formed between the polysilicon layer 26 and the N-diffusion layer 9. A polysilicon layer 28 is formed so as to sandwich it with an insulating film 27 in between.

Further, 29 and 30 are insulating films covering the polysilicon layer 24 and the polysilicon layer 26, respectively.

By arranging the polysilicon layers 26 and 28 overlappingly on the N-diffusion layer 9 of the capacitive part in this way, when the fiL level signal "0" is written into the MOS transistor,
The polysilicon layer 26 connected to the N- diffusion layer 9 also has the same potential. On the other hand, by connecting the polysilicon layer 28 to the power supply line and constantly applying the power supply voltage Vcc, the charge accumulated in the insulating film 27 surrounded by the two polysilicon layers 26 and 28 is (Cz + e2 )(Vc
c-Vth)=2 Cox(Vcc Vth) and 碌υ
, is twice that of the conventional example shown in FIGS. 2 and 3. Here, C1 is the capacitance between the polysilicon layer 28 and the N- diffusion layer 9, and C2 is the capacitance between the polysilicon layer 28 and the polysilicon layer 26. In the case of a grounded memory cell configuration, the above charges are accumulated when the H level signal ItO11 is written.

Next, one method of forming such a structure will be explained using FIG. 5.

First, the surface of the P-type silicon substrate 50 is thinly oxidized, a nitride film is formed, and normal LOGO8 oxidation is performed, and then ions are implanted using the photoresist film as a mask to form a region surrounded by the element isolation insulating film 6. An N-diffusion layer 9 is formed (FIG. 5(4)). In this case, the N- diffusion layer 90 is aligned with respect to the end A of the element isolation insulating film 6. In addition,
31 is a thin oxide film.

Next, an oxide film (SiOz) 32 and a nitride film (Si3
¥4'.

After forming the first insulating film 33, a polysilicon layer 34 as a first polysilicon layer is formed and phosphorus treatment is performed (FIG. 5(B)).

Further, after forming an oxide film 35, a nitride film 36, and a polysilicon layer 37 as a second polysilicon layer, anisotropic RIE etching is performed using a photoresist film as a mask.
(Reactive Ion Etching) to vertically cut and remove a part of each layer (Figure 5(C))
. The alignment at this time is performed with respect to the end B of the N-diffusion layer 9, and the distance between the cut end surface and the B surface is about 1 μm.

Next, a side wall made of an insulating film and a side wall made of a polysilicon layer are formed on the end face by a self-line method. To do this, first, a 5i02 film is formed on the entire surface as shown by the broken line by CVD, and then this S L
Only the O2 film is selectively etched as shown by A1 → A2 → A3, and an oxide film 32 and a nitride film 33 as a first insulating film are formed on the boundary between the end face and the exposed part of the N- diffusion M9.
A side wall 38 is formed to cover the end faces of the first polysilicon layer 34, the oxide film 35 and the nitride film 36 as the second insulating film, and a part of the exposed portion of the N- diffusion layer 9 (FIG. 5). (
D)).

In this case, the dimension a of the remaining sidewall 38 covering the N- diffusion layer 9 is always the same as the 5iO
Since it is equal to the thickness b of the z film, it can be easily controlled by the thickness b of the SiO2 film. In this example, a is 0.2 to 0.5
Let it be μm. Next, a polysilicon layer was formed on the entire surface as shown by the broken line, and after a phosphorus treatment, only this polysilicon layer was selectively etched by RIE.
A second polysilicon layer 37 covers the sidewall 38 made of the film.
A side wall 39 is formed to connect the end face of the N-diffusion layer 9 to the remaining exposed portion of the N-diffusion layer 9 (see FIG. 5).
The dimension C of the portion covering the N- diffusion layer 9 can be controlled by the thickness of the initial polysilicon layer. In this example, C was set to 0.2 to 0.5 μm similarly to a.

Next, wet oxidation is performed on the entire structure. As a result, a thick oxide film 40 is formed on the second polysilicon layer 3T due to the phosphorus treatment as described above, and a thin oxide film 41 is formed on the gate surface (see FIG. 5). ). Here, 23 and 30 in FIG. 4 correspond to 41 and 40, respectively, in the above description.

After that, according to the normal MOS D/RAM manufacturing method,
After performing ion implantation for vth control, deposition and phosphorus treatment of the polysilicon layer 24 for the gate, polysilicon etching and light oxidation for forming the source/drain are performed, and then a drain region is formed by ion implantation. 21 and 22, and a passivation film 25 made of PSG, etc., to form the fourth layer.
An element as shown in the figure can be formed. The first polysilicon layer 34 forms a polysilicon layer 28, and the second polysilicon layer 3T and sidewalls 39 form an N~diffusion layer 9.
A polysilicon layer 26 connected to the wafer is formed. Also, a first insulating film, which is also the oxide film 32 and the nitride film 33, a side wall 38, and a second insulating film, which is the oxide film 35 and the nitride film 36,
The insulating film 27 is formed by the insulating film.

It is also possible to further form a polysilicon layer on top of such a double-layered polysilicon oil to form a triple-layered structure, thereby increasing the charge storage ability three times.

FIG. 6 shows such an example. In other words, in this embodiment, the polysilicon layer 28 connected to the power source is branched into two stages, and the polysilicon layer 26 connected to the N- diffusion layer 9 is sandwiched between the two branches. Therefore, the capacitance is the capacitance C1 between the lower polysilicon layer 28a and the N- diffusion layer 9, the lower polysilicon Jff28a
and the capacitance C2 between the upper polysilicon layer 28b and the polysilicon layer 26, and the capacitance C2 between the upper polysilicon layer 28b and the polysilicon layer 26.
In the case of a Vcc applied memory configuration, the charge accumulated when writing a ``1'' level, and in the case of a grounded memory configuration, the charge accumulated when writing a ``1'' level is (C1+C2+C3X).
Vcc - Vth): 3 Cox (Vcc - Vth).

It is clear that the configuration described above can also be applied to a P-channel MOS memory in which memory cells are formed on an N-type substrate or N-well.

〔Effect of the invention〕

As explained above, according to the present invention, a polysilicon layer having the same potential as the semiconductor layer is disposed on the semiconductor layer of the opposite conductivity type provided in the semiconductor substrate or well layer under the memory insulating film, and Another polysilicon layer is placed between the silicon layer and the semiconductor layer with an insulating film in between, and this is connected to the vCC power line or memory cell ground.
By connecting it to MO8, the charge storage ability can be strengthened without using a group structure.
It is possible to improve the integration density of dynamic memory. Further, according to the manufacturing method of the present invention, the first and second polysilicon layers are formed on a semiconductor layer of opposite conductivity type formed on a semiconductor substrate or a well layer with an insulating film interposed therebetween, and then covered with the first and second polysilicon layers. By using a method in which the formed silicon insulating film and polysilicon layer are respectively processed using anisotropic etching to connect the second polysilicon end face and the semiconductor layer with the sidewalls of the polysilicon, It is possible to manufacture an MO8 type dynamic memory with polysilicon layers with a multi-layered structure.
This is extremely effective in improving the degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of an MO8 type dynamic memory, FIG. FIG. 4 is a sectional view of an MO8 type dynamic memory showing an embodiment of the present invention; FIGS. It is a sectional view of an MO8 type dynamic memory showing another embodiment of the invention. 5... P-type silicon substrate or P-well layer, 9...
...N-diffusion layer, 21, 22...Φ source/drain layer, 24...polysilicon layer (gate) 26...
・Polysilicon layer with the same potential as the N- diffusion layer, 2T...
Insulating film, 28...Polysilicon layer connected to power supply line, 32.φ...Oxide film forming first insulating film, 3
3.φ... Nitride film forming the first insulating film, 34...
・First polysilicon layer, 35... Oxide film forming the second insulating film, 36... Nitride film forming the second insulating film, 37... ψ Second polysilicon Layer, 38...
... Side wall made of insulating film, 39... Side wall made of e polysilicon. Agent Patent Attorney Akio Takahashi Figure 4 Figure 6 Figure 5

Claims (1)

[Claims] 1. In an MO8 type dynamic memory in which a semiconductor layer of an opposite conductivity type is provided on a semiconductor substrate or a shell layer under a memory insulating film, a polysilicon layer having the same potential as the semiconductor layer is provided on the semiconductor layer. An MO8 type dynamic memory characterized in that, at the same time, another polysilicon layer connected to a power supply line is disposed between the polysilicon layer and the semiconductor layer with an insulating film interposed therebetween. 2. A first insulating film, a first polysilicon layer, a second insulating film, and a second polysilicon layer are sequentially stacked on a semiconductor layer of opposite conductivity type formed on a semiconductor substrate or a well layer. a step of cutting and removing a portion of each of these layers to expose an end portion of the semiconductor layer; and a step of covering the entire surface of the semiconductor substrate with an insulating film and then subjecting the insulating film to anisotropic etching. forming a sidewall covering a part of the exposed portion of each end surface at the border between the cut end surface of the first insulating film, the first polysilicon layer, and the second insulating film and the exposed portion of the semiconductor layer; After covering the entire surface of the semiconductor substrate with a polysilicon layer, the polysilicon layer is subjected to anisotropic etching to cover the sidewalls made of the insulating film and to connect the cut end surface of the second polysilicon layer with the semiconductor layer. A method for manufacturing an MO8 type dynamic memory, comprising the step of forming a side wall connecting the remaining exposed portion.