JPS5918484U - hierarchical electronic circuit - Google Patents
hierarchical electronic circuitInfo
- Publication number
- JPS5918484U JPS5918484U JP11327782U JP11327782U JPS5918484U JP S5918484 U JPS5918484 U JP S5918484U JP 11327782 U JP11327782 U JP 11327782U JP 11327782 U JP11327782 U JP 11327782U JP S5918484 U JPS5918484 U JP S5918484U
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- wiring board
- hierarchical
- layer
- circuit assembly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の電子回路の一例を示す展開図、第２
図及び第３図はこの考案の電子回路の別の態様を示す側
面図、第４図は電子回路の更に別の態様を示す断面斜視
図である。
図において、１・・・・・・基板（電子回路組立配線板
）、２・・・・・・電子部品、３・・・・・・回路ブロ
ック、４・・・・・・折曲線、５・・・・・・回路連絡
用パターン、６，７・・・・・・絶縁材である。Figure 1 is a developed diagram showing an example of the electronic circuit of this invention;
3 and 3 are side views showing another embodiment of the electronic circuit of this invention, and FIG. 4 is a sectional perspective view showing still another embodiment of the electronic circuit. In the figure, 1... Board (electronic circuit assembly wiring board), 2... Electronic components, 3... Circuit block, 4... Folded line, 5 . . . Circuit connection pattern, 6, 7 . . . Insulating material.
Claims (1)
接続する電子回路を配線するとともに、電子回路組立配
線板を階層状に折曲し、各層間に絶縁処理を施して成る
階層状電子回路。 ２ 前記電子回路組立配線板の各層間に絶縁材を介在し
て成る実用新案登録請求の範囲第１項記載の階層状電子
回路。 ３ 前記電子回路組立配線板の各層間に絶縁材を充填し
て成る実用新案登録請求の範囲第１項記載の階層状電子
回路。[Scope of Claim for Utility Model Registration] 1. Wiring an electronic circuit to connect appropriate electronic components to a bendable electronic circuit assembly wiring board, and bending the electronic circuit assembly wiring board in a layered manner, and providing insulation between each layer. A hierarchical electronic circuit that is processed. 2. The hierarchical electronic circuit according to claim 1, wherein an insulating material is interposed between each layer of the electronic circuit assembly wiring board. 3. The hierarchical electronic circuit according to claim 1, wherein an insulating material is filled between each layer of the electronic circuit assembly wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11327782U JPS5918484U (en) | 1982-07-26 | 1982-07-26 | hierarchical electronic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11327782U JPS5918484U (en) | 1982-07-26 | 1982-07-26 | hierarchical electronic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5918484U true JPS5918484U (en) | 1984-02-04 |
Family
ID=30262281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11327782U Pending JPS5918484U (en) | 1982-07-26 | 1982-07-26 | hierarchical electronic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5918484U (en) |
-
1982
- 1982-07-26 JP JP11327782U patent/JPS5918484U/en active Pending
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