JPS59181722A - Electrostatic breakdown protecting circuit - Google Patents

Electrostatic breakdown protecting circuit

Info

Publication number
JPS59181722A
JPS59181722A JP5438583A JP5438583A JPS59181722A JP S59181722 A JPS59181722 A JP S59181722A JP 5438583 A JP5438583 A JP 5438583A JP 5438583 A JP5438583 A JP 5438583A JP S59181722 A JPS59181722 A JP S59181722A
Authority
JP
Japan
Prior art keywords
input
collector
base
emitter
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5438583A
Other languages
Japanese (ja)
Inventor
Hiroshi Enomoto
宏 榎本
Yasushi Yasuda
保田 康
Akinori Tawara
田原 昭紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5438583A priority Critical patent/JPS59181722A/en
Publication of JPS59181722A publication Critical patent/JPS59181722A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00307Modifications for increasing the reliability for protection in bipolar transistor circuits

Abstract

PURPOSE:To prevent a signal input stage of a bipolar type integrated circuit from electrostatic breakdown without dropping breakdown strength, by connecting the collector of a transistor and the emitter to an input terminal and an earth, respectively, and connecting a resistance of a specified value between the bas and the emitter. CONSTITUTION:An input clamp diode D becomes on when a negative voltage is applied to an input termianl, and prevents a fact that an abnormal negative voltage is applied to an input stage of an integrated circuit. When a positive voltage of an input IN rises excessively, breakdown is generated in a p-n junction between the collector and the base of an npn type TR Q, a part of a current flows to an earth through a resistance R, and the remaining current flows between the base and the emitter. By ths current, the TR Q is turned on, and in that case, a current flowing between the collector and the emitter in hFE times a current flowing between the collector and the base, therefore, by setting the hFE large, an abnormal current by overvoltage is by passed to an earth, and to say nothing of the collector - the base of the TR Q, electrostatic breakdown of the diode D, etc. is prevented. A value of the resistance R is related to input breakdown strength and electrostatic breakdown voltage, and set to 3-10KOMICRON.

Description

【発明の詳細な説明】 発明の技術分野 本発明は、バイポーラ型半導体集積回路の信号入力段を
静電破壊から保護する回路に関する。
TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit that protects a signal input stage of a bipolar semiconductor integrated circuit from electrostatic damage.

従来技術と問題点 バイポーラプロセスで製造される半導体装置の信号入力
段には、逆極性接続されたダイオードが広く用いられて
いる。例えば第1図に示すダイオード入力型のDTLロ
ジレクでは入力端INK、IN2とアース間にダイオー
ドDI、D2を、それらのアノードがアース、カソード
が入力端にくるように接続されている。本回路はダイオ
−F’ D 3 。
Prior Art and Problems Diodes connected with opposite polarities are widely used in the signal input stage of semiconductor devices manufactured using a bipolar process. For example, in the diode input type DTL LogiRec shown in FIG. 1, diodes DI and D2 are connected between the input terminals INK and IN2 and the ground so that their anodes are connected to the ground and their cathodes are connected to the input terminal. This circuit is a diode F'D3.

D4とトランジスタQ1.Q2でオープンコレクタ出力
型の2人力ナンドゲートを構成している。
D4 and transistor Q1. Q2 constitutes an open collector output type two-man powered NAND gate.

ダイオードDI、D2は入力INI、IN2に負電圧が
加わると導通して回路の異常動作を防止する目的で付け
られている入力クランプダイオードである。
The diodes DI and D2 are input clamp diodes provided for the purpose of preventing abnormal operation of the circuit by becoming conductive when a negative voltage is applied to the inputs INI and IN2.

かかる回路の問題点は、異常な正の高電圧が入力に加わ
った時、ダイオードDI、D2.D3゜D4がブレーク
ダウンを起こし該ダイオード′のPN接合に簗中的に電
流が流れるため、該ダイオードが熱的に破壊され易いと
いうことである。
The problem with such a circuit is that when an abnormally positive high voltage is applied to the input, the diodes DI, D2 . This means that the diode is likely to be thermally destroyed because D3 and D4 break down and a current flows through the PN junction of the diode.

発明の目的 本発明は、容易に破壊されずしかも入力段の耐圧を低下
させないで済む静電破壊保護回路を提供しようとするも
のである。
OBJECTS OF THE INVENTION The present invention seeks to provide an electrostatic discharge protection circuit that is not easily destroyed and does not require a reduction in the withstand voltage of the input stage.

発明の構成 本発明の静電破壊保護回路は、バイポーラ型半導体集積
回路の信号入力端子にトランジスタのコレフタをそして
アースに該トランジスタの工< ’7りを接続し、更に
該トランジスタのベース、エミッタ間に3〜IOKΩの
抵抗を接続してなることを特徴とするが、以下図示の実
施例を参照しながらこれを詳細に説明する。
Structure of the Invention The electrostatic discharge protection circuit of the present invention connects the collector of a transistor to the signal input terminal of a bipolar semiconductor integrated circuit, connects the base of the transistor to the ground, and further connects the collector between the base and emitter of the transistor. This is characterized in that a resistor of 3 to IOKΩ is connected to the resistor, and this will be explained in detail below with reference to the illustrated embodiment.

発明の実施例 第2図は本発明の一実施例を示す回路図で、Qは入力端
子INとアース間にコレクタ、エミッタ間を接続したn
pn型トランジスタ、Rはそのへ一部、エミッタ間に並
列に接続された入力抵抗である。このトランジスタQと
抵抗Rによって集積回路入力段の静電破壊を防止する保
護回路を構成する。Dは第1図のDI、D2と同じ人力
クランプダイオードで、入力端に負電圧が加わるときオ
ンになって、集積回路入力段に異常の負電圧が加わるの
を防止する。トランジスタQおよび抵抗Rからなる本発
明の保護回路は正の過電圧が加わるとき保護機能を発揮
する。即ち本回路では入力INの正電圧が過度に上昇す
るとトランジスタQのコレクタ、ベース間のpn接合に
ブレークダウンが生じ、一部の電流は抵抗Rを通してア
ースに流れ、残部の電流はベース、エミッタ間に流れる
。ベース、エミッタ間に電流が流れるとトランジスタQ
はオンし、そのコレクタ、エミッタ間に電流を流す。こ
のコレクタ、エミッタ間に流れる電流はコレクタ、ベー
ス間を流れる電流の11pB倍(hFEはトランジスタ
Qの電流増幅率)であるから、hFEを大きく (例え
ば100)設定することで過電圧による異常電流をアー
スへバイパスし、トランジスタQのコレクタ、ベース間
は勿論のことクランプダイオードD等の静電破壊を防止
することができる。
Embodiment of the Invention Figure 2 is a circuit diagram showing an embodiment of the present invention, where Q is an input terminal connected between the collector and the emitter between the input terminal IN and the ground.
A pn type transistor, R is an input resistor connected in parallel between its bottom and emitter. The transistor Q and the resistor R constitute a protection circuit for preventing electrostatic damage to the input stage of the integrated circuit. D is the same manual clamp diode as DI and D2 in FIG. 1, which turns on when a negative voltage is applied to the input terminal to prevent an abnormal negative voltage from being applied to the input stage of the integrated circuit. The protection circuit of the present invention consisting of transistor Q and resistor R performs a protection function when a positive overvoltage is applied. In other words, in this circuit, when the positive voltage at the input IN increases excessively, a breakdown occurs in the pn junction between the collector and base of transistor Q, and part of the current flows to ground through resistor R, and the remaining current flows between base and emitter. flows to When current flows between the base and emitter, the transistor Q
turns on, allowing current to flow between its collector and emitter. The current flowing between the collector and emitter is 11 pB times the current flowing between the collector and base (hFE is the current amplification factor of transistor Q), so by setting hFE to a large value (for example, 100), abnormal current caused by overvoltage can be grounded. This can prevent electrostatic damage not only between the collector and base of the transistor Q but also between the clamp diode D and the like.

抵抗Rの値は入力耐圧と静電破壊電圧に関係する。入力
耐圧は保護回路によるバイパス電流が流れるようになる
までの入力端INとアース間の耐圧を指し、Rの値が小
さい程トランジスタQのコレクタ、ベース間耐圧に近づ
く。極端な例はR−〇の場合で、このときはベース電流
が流れないのでトランジスタQは単なるダイオードと等
価になり、入力耐圧はトランジスタQ(7)C,B耐圧
それ自身となる。これに対しRの値が大きいと、入力耐
圧は低下する。これはコレクタ、ベース間のブレークダ
ウンによる電流の一部がトランジスタQのベース、エミ
ッタに流れて該トランジスタのコレクタ、エミッタ間に
主電流を流すためである。
The value of the resistor R is related to the input breakdown voltage and the electrostatic breakdown voltage. The input withstand voltage refers to the withstand voltage between the input terminal IN and the ground until a bypass current starts flowing through the protection circuit, and the smaller the value of R, the closer it approaches the withstand voltage between the collector and the base of the transistor Q. An extreme example is the case of R-0, in which case no base current flows, so the transistor Q becomes equivalent to a mere diode, and the input withstand voltage becomes the withstand voltage of the transistor Q (7) C, B itself. On the other hand, when the value of R is large, the input breakdown voltage decreases. This is because a part of the current due to the breakdown between the collector and the base flows to the base and emitter of the transistor Q, and the main current flows between the collector and the emitter of the transistor.

このような理由からでは、高電圧が加わって一旦トラン
ジスタQのC,Bがブレークダウンしてから耐圧低下が
生じることになるが、ベースに電荷があったりするとこ
の電荷かベース電流を流すので、C,Bブレークダウン
が生じなくても耐圧低下が起る。第3図はこのことを実
証する実験データで、横軸は抵抗Rの値、縦軸は入力耐
圧BVである。耐圧低下はR−■で最も著しい。
For this reason, once a high voltage is applied and C and B of transistor Q break down, the withstand voltage will drop, but if there is a charge at the base, this charge will cause the base current to flow. C, B A decrease in breakdown voltage occurs even if breakdown does not occur. FIG. 3 shows experimental data proving this, where the horizontal axis is the value of the resistance R, and the vertical axis is the input breakdown voltage BV. The breakdown voltage drop is most significant in R-■.

静電破壊電圧は入力端に静電気などによる高電圧パルス
が加わった場合に回路素子が熱破壊を生じる電圧をい\
、この静電破壊はR=OとしてトランジスタQのベース
、エミッタ間をショートしたときに最も低い。これはト
ランジスタQが単なるダイオードとしてしか機能できず
、そのコレクタ、ベース接合の熱的破壊電圧が静電破壊
電圧になるからである。これに対し、R−■とすればコ
レクタ、ベース間にブレークダウン電流が流れても、そ
れが全てベース電流となるのでトランジスタQのコレク
タ、エミッタ間に前記高電圧パルスによる入力電流の大
半が流れ、コレクタ、ベース接合に電流が集中して該接
合を破壊するという事態は回避できる。Rの抵抗値を数
にΩ以上にすると急激に破壊電圧Eは高くなる。第4図
はこれを実証する実験データで、横軸はRの抵抗値、縦
軸は静電破壊電圧Eである。
Electrostatic breakdown voltage is the voltage that causes thermal breakdown of circuit elements when a high voltage pulse due to static electricity is applied to the input terminal.
, this electrostatic discharge damage is lowest when the base and emitter of the transistor Q are short-circuited with R=O. This is because the transistor Q can only function as a diode, and the thermal breakdown voltage at its collector-base junction becomes the electrostatic breakdown voltage. On the other hand, if R-■, even if a breakdown current flows between the collector and the base, it will all become the base current, so most of the input current due to the high voltage pulse will flow between the collector and emitter of the transistor Q. , collector, and base junctions and destroy the junctions can be avoided. When the resistance value of R is increased to several Ω or more, the breakdown voltage E suddenly increases. FIG. 4 shows experimental data proving this, where the horizontal axis is the resistance value of R and the vertical axis is the electrostatic breakdown voltage E.

第3図および第4図から明らかなように、入力耐圧BV
と破壊電圧Eは抵抗Rの値に対し増減方向が逆である。
As is clear from Figures 3 and 4, the input breakdown voltage BV
The breakdown voltage E increases and decreases in the opposite direction to the value of the resistance R.

しかしR=3〜IOKΩにすれば、静電破壊電圧Eを高
くしかも入力耐圧BVの低下を回避することができる。
However, by setting R=3 to IOKΩ, it is possible to increase the electrostatic breakdown voltage E and avoid a decrease in the input breakdown voltage BV.

従って保護トランジスタQのベース抵抗RとしてはR=
3〜IOKΩが適当である。
Therefore, as the base resistance R of the protection transistor Q, R=
3 to IOKΩ is appropriate.

発明の効果 以上述べたように本発明によれば、トランジスタのコレ
クタを入力端に、エミッタをアースに接続し、そしてベ
ースー、エミッタ間に抵抗Rを接続して該抵抗Rの値を
3〜IOKΩにすることでバイポーラ型集積回路の信号
入力段を、入力耐圧を低下させることなく静電破壊から
防止できる利点がある。
Effects of the Invention As described above, according to the present invention, the collector of the transistor is connected to the input terminal, the emitter is connected to the ground, and a resistor R is connected between the base and the emitter, and the value of the resistor R is set to 3 to IOKΩ. This has the advantage that the signal input stage of the bipolar integrated circuit can be protected from electrostatic damage without lowering the input withstand voltage.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はバイポーラ型集積回路の入力段に設けられる内
部ゲートの一例を示す回路図、第2図は本発明の一実施
例を示す回路図、第3図および第4図は入力耐圧および
静電静電破壊電圧の入力抵抗値依存性を示す特性図であ
る。 図中、Qはトランジスタ、Rは入力抵抗である。 出願・人 富士通株式会社 代理人弁理士   青   柳     稔第1図 cc 第2図
Fig. 1 is a circuit diagram showing an example of an internal gate provided in the input stage of a bipolar integrated circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Figs. 3 and 4 show input breakdown voltage and static FIG. 3 is a characteristic diagram showing the dependence of electrostatic breakdown voltage on input resistance value. In the figure, Q is a transistor and R is an input resistance. Application/Person Minoru Aoyagi, Fujitsu Ltd. Representative Patent Attorney Figure 1 cc Figure 2

Claims (1)

【特許請求の範囲】[Claims] バイポーラ型半導体集積回路の信号入力端子にトランジ
スタのコレクタをそしてアースに該トランジスタのエミ
ッタを接続し、更に該トランジスタのベース、エミッタ
間に3〜IOKΩの抵抗を接続してなることを特徴とす
るバイポーラ型半導体S積回路の信号入力段の静電破壊
保護回路。
A bipolar semiconductor integrated circuit, characterized in that the collector of the transistor is connected to the signal input terminal of the bipolar semiconductor integrated circuit, the emitter of the transistor is connected to the ground, and a resistor of 3 to IOKΩ is further connected between the base and emitter of the transistor. Electrostatic damage protection circuit for the signal input stage of a type semiconductor S-product circuit.
JP5438583A 1983-03-30 1983-03-30 Electrostatic breakdown protecting circuit Pending JPS59181722A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5438583A JPS59181722A (en) 1983-03-30 1983-03-30 Electrostatic breakdown protecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5438583A JPS59181722A (en) 1983-03-30 1983-03-30 Electrostatic breakdown protecting circuit

Publications (1)

Publication Number Publication Date
JPS59181722A true JPS59181722A (en) 1984-10-16

Family

ID=12969211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5438583A Pending JPS59181722A (en) 1983-03-30 1983-03-30 Electrostatic breakdown protecting circuit

Country Status (1)

Country Link
JP (1) JPS59181722A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335922A (en) * 1992-05-28 1993-12-17 Sanyo Electric Co Ltd Photodetector
JPH09293836A (en) * 1996-04-25 1997-11-11 Rohm Co Ltd Semiconductor device
KR19980058496A (en) * 1996-12-30 1998-10-07 김영환 Electrostatic Discharge Circuit of Semiconductor Devices
US6392463B1 (en) 2000-07-07 2002-05-21 Denso Corporation Electrical load driving circuit with protection
DE10046668B4 (en) * 1999-09-20 2011-03-31 DENSO CORPORATION, Kariya-shi Electric load control circuit with protective device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05335922A (en) * 1992-05-28 1993-12-17 Sanyo Electric Co Ltd Photodetector
JPH09293836A (en) * 1996-04-25 1997-11-11 Rohm Co Ltd Semiconductor device
KR19980058496A (en) * 1996-12-30 1998-10-07 김영환 Electrostatic Discharge Circuit of Semiconductor Devices
DE10046668B4 (en) * 1999-09-20 2011-03-31 DENSO CORPORATION, Kariya-shi Electric load control circuit with protective device
US6392463B1 (en) 2000-07-07 2002-05-21 Denso Corporation Electrical load driving circuit with protection

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