JPS59181469U - electronic learning device - Google Patents
electronic learning deviceInfo
- Publication number
- JPS59181469U JPS59181469U JP7459483U JP7459483U JPS59181469U JP S59181469 U JPS59181469 U JP S59181469U JP 7459483 U JP7459483 U JP 7459483U JP 7459483 U JP7459483 U JP 7459483U JP S59181469 U JPS59181469 U JP S59181469U
- Authority
- JP
- Japan
- Prior art keywords
- learning device
- electronic learning
- hints
- correct
- answer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrically Operated Instructional Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の電子学習装置の一実施例を示すブロッ
ク図、第２図は同じ（ＲＯＭ７の記憶状態を示す図、第
３図はキー人力部１の各キー１ａ〜１ｅの操作とその結
果表示部２に表示されるパターンの一例を示す図である
。
１・・・・・・キー人力部、２・・・・・・表示部、３
・・・・・・制御路、５・・・・・・アドレスデータレ
ジスタ、６・・・用アドレス指定回路、７・・・・・・
ＲＯＭ、 ８・・・・・・表示レジスタ、１０・・・・
・・正解レジスタ、１１・・・・・・判断回路′、１３
・・・・・・解答レジスタ、１４・・・・・・アドレス
データ記憶部。FIG. 1 is a block diagram showing one embodiment of the electronic learning device of the present invention, FIG. 2 is the same (a diagram showing the storage state of the ROM 7, and FIG. It is a diagram showing an example of a pattern displayed on the result display section 2. 1... Key human power section, 2... Display section, 3
...Control path, 5...Address data register, 6...Address designation circuit, 7...
ROM, 8...Display register, 10...
...Correct answer register, 11...Judgment circuit', 13
. . . Answer register, 14 . . . Address data storage unit.
Claims (1)
る手段と、このヒントを順次表示する手段と、当該ヒン
トより連想されて入力された解答の正誤を判断する手段
と、この正誤の結果を表示する手段とよりなる電子学習
装置。A means for storing a plurality of answers and hints corresponding to each answer, a means for sequentially displaying the hints, a means for determining whether an input answer associated with the hints is correct, and a means for determining whether the input answer is correct or incorrect. An electronic learning device consisting of a display means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7459483U JPS59181469U (en) | 1983-05-20 | 1983-05-20 | electronic learning device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7459483U JPS59181469U (en) | 1983-05-20 | 1983-05-20 | electronic learning device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59181469U true JPS59181469U (en) | 1984-12-04 |
Family
ID=30204682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7459483U Pending JPS59181469U (en) | 1983-05-20 | 1983-05-20 | electronic learning device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181469U (en) |
-
1983
- 1983-05-20 JP JP7459483U patent/JPS59181469U/en active Pending
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