JPS59177795A - Memory testing method - Google Patents

Abstract

PURPOSE:To shorten time for testing for degeneracy and interference in relation to testing method for finding interference and degeneracy between addresses of 2d bit memory. CONSTITUTION:In each step i (i is from 0 to d-1), d-1-i th digit Ad-1-i when A (A=0-2d-1) is denoted in binary system, is written in the address A for each step, and it is confirmed that Ad-1-i can be read out from address 0-2d-1 which is the address after completion of writing of each step. In step 0, a value of uppermost digit when address 0-7 is expressed in binary system is written in each address 0-7. Then, data of address 0-7 are read out, and checked for interference and degeneracy between the value of any address in the block of address 0-3 and the value of any address in the block of address 4-7. If there is no interference and degeneracy, the value of second digit when address 0-7 is expressed in binary system is written in each address 0-7 in step 1. Then data of address 0-7 are read out, and similar operation is continued successively.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention Test method for discovering interference and degeneracy between addresses of the U2d hint memory of the present invention VC related, 1 trial 1 set 1ijjk
This invention relates to a memory test method that can be reduced by =r.

(bl) Prior art and problems Figure 1 is an example of a memory test;
The figure is a state diagram showing how each step of a conventional example is stored in a memory.

In the figure, 1 is the memory under test, 2 is the driver/receiver section, and 3 is the memory under test.
is the I10 board, 4 is the processor (hereinafter referred to as CPU)
, 5 is the memory, and 6 is the entire test element 1j'+4 program area.

The operation of the memory tester shown in FIG.
10 Input port of port 3 - 5 driver/v receiver = driver of B2 l Address bus When writing to and reading from the memory under test 1 via the data bus, the read address is sent from the CPU 4? I10 boat 3 input boat, driver
It is sent to the board test memo IJ1 via the driver care address bus of the receiver section 2, and the take of the address is sent to the board test memo IJ1 via the driver care address bus of the receiver section 2.
- The bar, 110 boat 3, is launched via the output hooray,
This is to check whether the CPU 4-r:s[w is a take. Here, when testing a 2d bit memory under test, the address is 1. It is necessary to carry out a full test to see if there is a lot of interference, such as degeneracy in which the imported items are also transferred to addresses ■ and J, and interference by changing the address to the address ■.For this reason, conventionally, the following explanation was A program for executing the procedure is installed in the test procedure program area 6 and tested.

For convenience of explanation, the test procedure will be explained below assuming that 2d bits and 2d bits are 23-8 bits.

First, at 5tepO, l-1, as shown in Figure 2, Abilev is 0.
Write 1 to the address, insert 0 to addresses 1 to 7, then read addresses 0 to 7, check whether there is degeneracy interference, and perform the next 5 steps. Write 1 in the address, write 0 in addresses 0, 2 to 7, then 0
Read addresses ~7, check whether there is any degeneracy 1θ, and in the next 5 steps 2, write 1 to address 2@ as shown in Figure 2, and write 1 to 0. 1. Write 0 into addresses 3 to 7, read out addresses 0 to 7 by Φ°C, and check to see if there is any degenerate interference.Sequentially write, read, and read according to the same rule until step 7, and check if there is any degenerate interference. Do all the tests.

In such conventional testing methods, the above-mentioned procedure (
2d) There is a drawback that the number of times of writing and reading is large (two times), and a large amount of testing time is required.

(c) Object of the Invention The object of the present invention is to overcome the above-mentioned drawbacks and provide a memory testing method that can shorten the test time for determining the presence or absence of degenerate interference.

(d) Structure of the Invention The present invention achieves the above object/+: In order to perform a 2D bit memory testing method, 2 (To fully check for interference degradation in I bit memory, addresses are divided into two blocks). Divide into +J: in the block, check whether the value of the address 1 of the sudden address and the value of the address 1, e, of the other) lock is causing interference degeneracy. Divide the block into two sub-blocks, and check whether there is any mutual interference between the value of an arbitrary address in a sub-block in each block and the value of an arbitrary address in another sub-block. , it is sufficient to repeat the process until the sub-block divided into two becomes 1 bit, and for each progressive i (where i is from O to d-1), set the address to A to addresses 0 to 2d-1. When this A is expressed in binary, the d-1-i digits Ad-1-i are added at each step, and after the writing of each step is completed, Ad-1-i is added from addresses 0 to 2d-1. -1-i The device is characterized by having a means for confirming that cancer C can be extracted.

(e) Embodiment of the Invention An embodiment of the invention will be explained below with reference to the drawings. The third item 1 is a flowchart of the test procedure of the embodiment of the present invention,
Fig. 4 is a record of the writing of each stage in the memory of the fruit observation of the present invention.
je, address of protruding symmetry (0 to 2d-1), 2d is Ow, number of bits in test memory, Ad-" i is the number of digits to write address 8 in binary notation according to step 1. Then, step o, vvc=Ad-
1゜Ad-2--Ao, 1 in step 0 A
d-1 is the value of the most significant digit, Ad omitted by Stesive 1
2 is the number of the 24th digit, AO is the number of the least significant digit, 111↓
It is. For example, in 23-8, 1 to fd:A is O to 7, which is expressed in binary notation as 000, 001. ,01
0, 011.100°101, 110.111. Therefore, the most significant digit read by Stesive 0 is the address, 0
~ 3 is I"io, addresses 4 to 7 are 1, steady l
The second apricot digit written in is 0 for addresses 0, 1, and 4.5,
The address 2, 3° 6.7 is 1, the least significant digit of the address 0.2.4.6 in step 3 is 0, and the address 1, 3° 5.7 is 1.

In the case of the present invention, a program to be executed according to the flowchart shown in FIG. 3 is installed in the test procedure program area 6 of the memory 5 of the memory tester shown in FIG. 1, and the memory is tested. Explain the test procedure as a human. In this case, A is 0-7. This is 7 in binary
F is p as explained above, and the numerical values from the most significant digit to the least significant digit also follow the above theory. 1. At 5tep O, write the most significant digit value representing addresses 0 to 7 in binary to each address 0 to 7 as shown in Figure 4, and then write the value of the most significant digit to each address 0 to 7 as shown in Figure 4.
-7 Cheetara readout, all checks are made to see if there is any interference degeneracy between the value of the old address of the block of addresses 0-3 and the value of any address of the block of addresses 4-7. If there is no interference degeneracy, proceed to the next 5 steps.In step 1, write each address 0 to 7 VC, the second digit of addresses 0 to 7 expressed in binary as shown in Figure 4, and then write the data of addresses 0 to 7. Read out and check whether there is any interference between the value of any address in the address 0.1 block in the block of addresses θ~3 and the value of any address in addresses 2 or 3, or if there is any interference with the value of the address 0.1 block in the block with addresses θ~3. It is checked whether interference degeneracy is occurring between the value of any address in blocks 4 and 5 of address 7 in block 7 and the value 1 of any address in address 6.7. If there is no interference degeneracy, in step 3, the addresses 0 to 7 are expressed in binary notation, and the values of the least significant digits are enriched as shown in Figure 4.Then, the data at addresses θ to 7 is read out. , address 0, 1 block, 2, 3 block, 4, 5
Checking whether interference degeneracy has occurred in blocks 6 and 7. The test for the presence or absence of interference degeneracy is completed.

In this way, the number of write and read times is 1l-i8X3
= 24 times, that is, 2dxd, which means that the number of readings is less than in the conventional case, and the test time is shortened. This difference becomes larger than in the conventional case until the value of d becomes large.

(f) Effects of the Invention As explained in detail above, the present invention has the effect of reducing the total test time for testing the integrity of memory interference degeneracy, and this effect becomes more pronounced as the number of bits of the memory increases. big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a memory tester, FIG. 2 is a state diagram of the memory insertion of each step in the conventional example, and FIG. 3 is a flowchart of the test+order of the embodiment of the present invention. FIG. 4 is a diagram showing the state in which the valley step is embedded into the memory according to the embodiment of the present invention. In the figure, 1 is the memory under test, 2 is the driver/receiver section, and 3 is the memory under test.
is the I10 port, 4 is the processor, 5 is the memory, 6 is the test procedure program area, i is the step number, A is the address, 2d is the number of bits of the memory under test, A d -1-j
is the numerical value of the digit in which the address A'4i expressed in binary notation is written according to step i.

Claims (1)

[Claims] In the 2D focus memory test method, each step 1 (
However, +Di O to d-1), and d- when this A is expressed in binary notation at address A (A-〇~2d-1).
1-i digit Ad-1-i is written for each valley stenog, and after writing of each step is completed, address 0 to 26-],
1:9 Ad-+-I is equipped with one stage of memory that can read Ad-+-i.