JPS59175727A - Plasma etching apparatus - Google Patents

Plasma etching apparatus

Info

Publication number
JPS59175727A
JPS59175727A JP5072283A JP5072283A JPS59175727A JP S59175727 A JPS59175727 A JP S59175727A JP 5072283 A JP5072283 A JP 5072283A JP 5072283 A JP5072283 A JP 5072283A JP S59175727 A JPS59175727 A JP S59175727A
Authority
JP
Japan
Prior art keywords
lower electrode
plasma etching
etching apparatus
semiconductor wafer
holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5072283A
Other languages
Japanese (ja)
Inventor
Taiichi Otani
泰一 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5072283A priority Critical patent/JPS59175727A/en
Publication of JPS59175727A publication Critical patent/JPS59175727A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/34Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3411Constructional aspects of the reactor
    • H01J37/3435Target holders (includes backing plates and endblocks)

Abstract

PURPOSE:To uniform the physical characteristics of semiconductor wafer at the holding place and obtain the uniform etching characteristic by disposing the coolant path not only to the circumferencial side of lower electrode but also at the center side thereof. CONSTITUTION:A coolant path 23 is guided to the area near the circumference of electrode 21 along the circumference of semiconductor wafer holding place 221 from the coolant path entrance 23a provided at the center of lower electrode 21 and it is thereafter disposed along the external half circumference of the wafer holding positions 221-226. Moreover, the path 23 is folded to the inside along the circumference of the holding position 226 and then extended along the internal half circumference of the holding positions 226-221. Thereafter, it is disposed so that it is fed back to the coolant path exit 23b provided at the center of electrode 21. Since the path 23 is almost symmetrically disposed respectively to the holding places 221-226, the physical characteristics are uniformed within the range of respectively holding positions 221-226 and uniformly of etching rate can be improved.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はI C、LSI等の半導体装置の製造に使用さ
れるプラズマエツチング装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in plasma etching equipment used for manufacturing semiconductor devices such as ICs and LSIs.

〔発明の技術的背景〕[Technical background of the invention]

第1図は従来のプラズマエツチング装置の一例を示す断
面図である。同図において、1はステンレス製の真空容
器である。該真空容器1の一部をなすように、平行平板
電極を構成する上部電極2と下部電極3が対向して配設
されている。この上部電極および下部電極2,3は、夫
夫テフロンリング4,5にょシ真空容器1と電気的に絶
縁されている。また、上部電極2にはガス導入管6が連
結されておシ、真空容器1には例えば油拡散ポンプとロ
ータリーポンプを有する排気系に連結された排気管7が
設けられている。他方、下部電極3には高周波電源8が
接続され、上部電極2および真空容器1は接地されてい
る。更に1下部電極3上にはカーボンサセグタ9が設け
られ、該サセプタ9上にエツチングされるべき半導体ウ
ェハー10が載置される。カーがンサセプタ9を設ける
のは、半導体ウェハー10の重金属汚染を防止するため
である。そして、下部電極3の下面には冷却用の水冷管
11が配設され、まだ上部電極2にも同様の水冷管12
が配設されている。
FIG. 1 is a sectional view showing an example of a conventional plasma etching apparatus. In the figure, 1 is a vacuum container made of stainless steel. An upper electrode 2 and a lower electrode 3, which constitute parallel plate electrodes, are arranged to face each other so as to form a part of the vacuum vessel 1. The upper and lower electrodes 2 and 3 are electrically insulated from the vacuum vessel 1 and the Teflon rings 4 and 5. Further, a gas introduction pipe 6 is connected to the upper electrode 2, and an exhaust pipe 7 is provided to the vacuum vessel 1, which is connected to an exhaust system having, for example, an oil diffusion pump and a rotary pump. On the other hand, a high frequency power source 8 is connected to the lower electrode 3, and the upper electrode 2 and the vacuum vessel 1 are grounded. Further, a carbon susceptor 9 is provided on the first lower electrode 3, and a semiconductor wafer 10 to be etched is placed on the susceptor 9. The reason why the susceptor 9 is provided is to prevent heavy metal contamination of the semiconductor wafer 10. A water cooling pipe 11 for cooling is provided on the lower surface of the lower electrode 3, and a similar water cooling pipe 12 is also provided on the upper electrode 2.
is installed.

上記プラズマエツチング装置の使用に際し、ガス導入管
6から真空容器1内に導入されたCF4尋の反応ガスは
、平行平板電極2,3間の高周波電界によりプラズマ化
され、該プラズマガスは半導体ウェハー12と反応して
エツチングを打力っだ後、排気管7から系外に排出され
る。
When using the above-mentioned plasma etching apparatus, 4 fathoms of CF reaction gas introduced into the vacuum vessel 1 from the gas introduction pipe 6 is turned into plasma by the high frequency electric field between the parallel plate electrodes 2 and 3, and the plasma gas is applied to the semiconductor wafer 12. After reacting with the etching force, it is discharged from the system through the exhaust pipe 7.

ところで、上記従来のプラズマエツチング装置において
、下部電極3の下面の水冷管11は第2図に示すように
配設されている。図示のように、半導体ウェハー10は
下部電極3の周縁内側に沿って複数載置されるようにな
っている。
Incidentally, in the conventional plasma etching apparatus described above, the water cooling pipe 11 on the lower surface of the lower electrode 3 is arranged as shown in FIG. As shown in the figure, a plurality of semiconductor wafers 10 are placed along the inner side of the periphery of the lower electrode 3.

そして、水冷管11は下部電極3の中心に設けた水冷管
入口11aから内部電極3の半径方向妊延設され、半導
体ウェハー10・・・の外側半周に沿って配管された後
に再び下部電極3の中心に設けた冷水管出口11bに帰
還するように配設されている。従って、半導体ウェハー
10・・・の内側半周部分には冷水管11は配設されて
いない。
Then, the water-cooled pipe 11 is installed in the radial direction of the internal electrode 3 from the water-cooled pipe inlet 11a provided at the center of the lower electrode 3, and is piped along the outer half circumference of the semiconductor wafer 10. The cold water pipe is arranged so as to return to the cold water pipe outlet 11b provided at the center of the pipe. Therefore, the cold water pipe 11 is not provided in the inner half circumference of the semiconductor wafers 10 .

〔背景技術の問題点〕 上記のように、従来のプラズマエツチング装置では、下
部電極下面の冷水管11が半導体ウェハーの載置位置に
おいて非対称に配設されていたため、冷水管1ノが配設
されている電極周縁側と冷水管11が配設されていない
電極中心側とでウェハー載置位置如物理的特性の不均一
が生じていた。この場合に不均一を生じる物理特性とし
ては温度の他、冷水管1ノ内の水の影響によって下部電
極3のインピーダンスにも不均一を生じる。このため、
ウエノ・−載置位置付近の電位分布に不均一を生じるこ
とから、下部電極3の外周側と中心側とで半導体ウェハ
ーのエツチング速度が異なることとなシ、均一なエツチ
ングができないという問題があった。
[Problems in the Background Art] As described above, in the conventional plasma etching apparatus, the cold water pipes 11 on the lower surface of the lower electrode are arranged asymmetrically at the mounting position of the semiconductor wafer. The physical characteristics of the wafer were non-uniform between the peripheral edge of the electrode where the cold water pipe 11 was not provided and the center side of the electrode where the cold water pipe 11 was not provided. In this case, the physical characteristics that cause non-uniformity include not only the temperature but also the impedance of the lower electrode 3 due to the influence of water in the cold water pipe 1. For this reason,
Ueno - Since the potential distribution in the vicinity of the mounting position is non-uniform, the etching speed of the semiconductor wafer differs between the outer peripheral side and the center side of the lower electrode 3, and there is a problem that uniform etching cannot be performed. Ta.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に鑑みてガされたもので、下部電極に
おける冷媒通路の配設パターンを改良するととによシ半
導体ウェハー載置位置における物理特性を均一化し、も
って均一なエツチング特性が得られるプラズマエツチン
グ装置を提供するものである。
The present invention was developed in view of the above circumstances, and it is possible to improve the arrangement pattern of the coolant passages in the lower electrode to uniformize the physical characteristics at the semiconductor wafer mounting position, thereby obtaining uniform etching characteristics. A plasma etching apparatus is provided.

〔発明の概要〕[Summary of the invention]

本発明によるプラズマエツチング装置は、冷却用の冷媒
通路を設けた下部電極上にカーがンサセプタを介して同
時に複数の半導体ウエノ・−を載置し、該半導体ウエノ
・−のプラズマエツチングを行なう平行平板型プラズマ
エツチング装置において、前記冷媒通路を前記半導体ウ
エノ1−載置位置の周縁に沿って前記下部電極の周縁側
だけでなく中心側にも配設したことを特徴とするもので
ある。
The plasma etching apparatus according to the present invention is a parallel plate in which a plurality of semiconductor wafers are simultaneously placed on a lower electrode provided with a refrigerant passage for cooling via a susceptor, and the semiconductor wafers are plasma etched. The plasma etching apparatus is characterized in that the coolant passage is disposed not only on the periphery side of the lower electrode but also on the center side along the periphery of the semiconductor wafer 1-mounting position.

上記本発明のプラズマエツチング装置では、半導体ウエ
ノ・−載置位置での冷媒通路の対称性が改善されるため
、物理的特性の均一化が図れ、従って均一なエツチング
特性を得ることができる。
In the plasma etching apparatus of the present invention, the symmetry of the refrigerant passage at the semiconductor wafer mounting position is improved, so that physical characteristics can be made uniform, and therefore uniform etching characteristics can be obtained.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明によるプラズマエツチング装置ノー実施例
について説明する。
Hereinafter, a non-embodiment of the plasma etching apparatus according to the present invention will be described.

第3図は本発明の一実施例になるプラズマエツチング装
置において、下部電極での冷媒通路の配設パターンを示
す平面図である。同図において、21は下部電極であり
、22+ 〜22゜は半導体ウエノ・−の載置位置であ
る。冷媒通路23は下部電極21の中心に設けられた冷
媒通路人口23hから半導体ウニノル−載置位置221
の周縁に沿って下部電極21の周縁近傍まで引き出され
た後、ウエノ・−載置位置21+ 〜226の外側半周
に沿って波状に配設されている。
FIG. 3 is a plan view showing an arrangement pattern of coolant passages in a lower electrode in a plasma etching apparatus according to an embodiment of the present invention. In the figure, 21 is a lower electrode, and 22+ to 22 degrees are mounting positions for the semiconductor wafer. The refrigerant passage 23 is connected from the refrigerant passage 23h provided at the center of the lower electrode 21 to the semiconductor mounting position 221.
After being drawn out to the vicinity of the periphery of the lower electrode 21 along the periphery of the wafer, they are arranged in a wavy manner along the outer half of the wafer mounting positions 21+ to 226.

更に、冷媒通路23はウエノ・−載置位置2211の周
縁に沿って内側に折り返され、今度はウェハー載置22
6〜22にの内側半周に沿って延設された後、下部電極
21の中心部に設けられた冷媒通路出口23bFC帰還
するように配設されている。
Furthermore, the coolant passage 23 is turned inward along the periphery of the wafer placement position 2211, and this time the coolant passage 23
The refrigerant passage outlet 23bFC is disposed at the center of the lower electrode 21 and returns to the refrigerant passage outlet 23bFC.

この実施例のプラズマエツチング装置は、下部電極21
の冷媒通路23が上記のように配設されている点を除き
、第1図の従来のプラズマエツチング装置と同様の構成
になっている。
The plasma etching apparatus of this embodiment has a lower electrode 21
The structure is similar to that of the conventional plasma etching apparatus shown in FIG. 1, except that the coolant passage 23 is arranged as described above.

上記実施例のプラズマエツチング装置を用い、これを半
導体ウェハーのエツチングに適用した例について説明す
る。
An example in which the plasma etching apparatus of the above embodiment is applied to etching a semiconductor wafer will be described.

まず、第4図に示すエツチング試料を製作した。即ち、
直径4インチの単結晶クリコンウェハー31表面を熱酸
化して膜厚1000Xの酸化膜32を形成した。続いて
、7ラン(5in4)の熱分解(750℃)を用いた減
圧気相成長法(LPGVD )により多結晶シリコン層
を堆積し、更[1000℃で燐を拡散して膜厚6000
Xのn型多結晶シリコ7層33を形成した。次いで、エ
ツチングマスクとなるIジ型しジス)zfターン34を
形成した。
First, an etching sample shown in FIG. 4 was prepared. That is,
The surface of a single crystal wafer 31 with a diameter of 4 inches was thermally oxidized to form an oxide film 32 with a thickness of 1000X. Subsequently, a polycrystalline silicon layer was deposited by low pressure vapor deposition (LPGVD) using 7 runs (5in4) of thermal decomposition (750°C), and then further deposited to a film thickness of 6000°C by diffusing phosphorus at 1000°C.
Seven layers 33 of n-type polycrystalline silicon of X were formed. Next, an I-shaped di-ZF turn 34 was formed to serve as an etching mask.

こうして製作された第4図のエツチング試料につき、前
記実施例のグラズマエッチング装置y従来のプラズマエ
ツチング装置とでエツチングを行なった。なお、何れの
場合もエツチング条件は次の通シである。
The thus produced etching sample shown in FIG. 4 was etched using the plasma etching apparatus of the above embodiment and a conventional plasma etching apparatus. In either case, the etching conditions are as follows.

・反応性ガス ct2: 20 SCCM H2: 6 SCCM ・圧力    10 Pa ・印加電力 13、56 MHz  t  0.25 W/cm2・
エツチング時間  3分間 上記プラズマエツチング後、エツチングされた試料を硫
酸と過酸化水素水との混液で処理しテV N ストz?
ターン34を除去した後、クリステップによシ多結晶シ
リコン層33のエツチング領域における膜厚番測定し、
との膜厚がもエツチング速度を求めた。第5図および第
1表はとのエツチング試験結果を輯ホ会≠示す。
・Reactive gas ct2: 20 SCCM H2: 6 SCCM ・Pressure 10 Pa ・Applied power 13.56 MHz t 0.25 W/cm2・
Etching time: 3 minutes After the above plasma etching, the etched sample was treated with a mixture of sulfuric acid and hydrogen peroxide solution.
After removing the turn 34, the film thickness in the etched region of the polycrystalline silicon layer 33 is measured using a crystal step.
The etching rate was also determined by the film thickness. FIG. 5 and Table 1 show the results of the etching test.

第  1  表 なお、第5図は下部電極の中心とエツチングマスク置位
置 ルエッチング速度を示しておシ、AおよびB[夫々第2
図および第3図のA点、B点に対応している。
Table 1 Note that FIG. 5 shows the etching speed of the center of the lower electrode and the etching mask position.
This corresponds to points A and B in the figure and FIG.

この試験結果から、上述した実施例のプラズマエツチン
グ装置では冷媒通路23を半導体ウェハーの載置位置2
2.〜226の夫々に対して略対象に配置しているため
、個々のウェハー載置位置22.〜226の範囲内で物
理特性が均一化され、エツチング速度の均一性が向上し
ていることが明らかになった。
From this test result, in the plasma etching apparatus of the above-mentioned embodiment, the coolant passage 23 is located at the semiconductor wafer mounting position 2.
2. Since the wafers are arranged substantially symmetrically with respect to each of the wafer placement positions 22. It was revealed that the physical properties were made uniform within the range of ~226, and the uniformity of the etching rate was improved.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように、本発明によればプラズマエツチン
グ装置における物理特性の均一化を図シ、もって工7チ
ング速度のばらつきを抑えることができる等、顕著々効
果を得ることができる。
As described in detail above, according to the present invention, it is possible to obtain remarkable effects such as uniformity of physical characteristics in a plasma etching apparatus, thereby suppressing variations in etching speed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプラズマエツチング1to−例を示す説
明図、第2図は従来のプラズマエツチング装置の下部電
極における冷水管配設ノJ?ターンを示す平面図、第3
図は本発明の一実施例になるプラズマエツチング装置の
下部電極における冷媒通路配設パターンを示す平面図、
第4図はエツチング試験に用いた試料を示す断面図、第
5図は本発明の一実施例になるプラズマエツチング装置
と従来のプラズマエツチング装置の夫々について行なっ
たエツチング試験の結果を比較して示す線図である。 2ノ・・・下部電極、221〜226・・・半導体ウェ
ハー載置位置、23・・・冷媒通路、23a・・・冷媒
通路入口、23b・・・冷媒通路出口。 出願人代理人  弁理士 鈴 江 武 彦第211 @311 第4− 藁5図
FIG. 1 is an explanatory diagram showing an example of conventional plasma etching, and FIG. 2 is an illustration of cold water pipe arrangement at the lower electrode of a conventional plasma etching apparatus. Plan view showing turn, 3rd
The figure is a plan view showing a coolant passage arrangement pattern in a lower electrode of a plasma etching apparatus according to an embodiment of the present invention;
Fig. 4 is a cross-sectional view showing the sample used in the etching test, and Fig. 5 shows a comparison of the results of etching tests conducted on a plasma etching apparatus according to an embodiment of the present invention and a conventional plasma etching apparatus. It is a line diagram. 2 No. Lower electrode, 221 to 226 Semiconductor wafer placement position, 23 Coolant passage, 23a Coolant passage inlet, 23b Coolant passage outlet. Applicant's agent Patent attorney Takehiko Suzue No. 211 @ 311 No. 4 - Figure 5

Claims (1)

【特許請求の範囲】[Claims] 冷却用の冷媒通路を設けた下部電極上にカーがンサセグ
タを介して同時に複数枚の半導体ウェハーを載置し、該
半導体ウエノ・−のプラズマエツチングを行なう平行平
板プラズマエツチング装置において、前記冷媒通路を前
記半導体ウェハー載置位置の周縁に沿って前記下部電極
の周縁側だけでなく中心側にも配設したことを特徴とす
るプラズマエツチング装置。
In a parallel plate plasma etching apparatus, a plurality of semiconductor wafers are simultaneously placed on a lower electrode provided with a refrigerant passage for cooling via a car sensor segmenter, and the semiconductor wafer is plasma etched. A plasma etching apparatus characterized in that the lower electrode is disposed along the periphery of the semiconductor wafer mounting position not only on the periphery side but also on the center side.
JP5072283A 1983-03-26 1983-03-26 Plasma etching apparatus Pending JPS59175727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5072283A JPS59175727A (en) 1983-03-26 1983-03-26 Plasma etching apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5072283A JPS59175727A (en) 1983-03-26 1983-03-26 Plasma etching apparatus

Publications (1)

Publication Number Publication Date
JPS59175727A true JPS59175727A (en) 1984-10-04

Family

ID=12866760

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5072283A Pending JPS59175727A (en) 1983-03-26 1983-03-26 Plasma etching apparatus

Country Status (1)

Country Link
JP (1) JPS59175727A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030540U (en) * 1983-08-03 1985-03-01 株式会社日立製作所 Cooling device for wafer loading table
JPS63311726A (en) * 1987-06-15 1988-12-20 Ulvac Corp Microwave plasma processor
US4859304A (en) * 1988-07-18 1989-08-22 Micron Technology, Inc. Temperature controlled anode for plasma dry etchers for etching semiconductor
WO2004093167A3 (en) * 2003-03-31 2005-06-09 Lam Res Corp Substrate support having temperature controlled surface
US7528073B2 (en) 2004-11-04 2009-05-05 Sumitomo Electric Industries, Ltd. Dry etching method and diffractive optical element
US7810506B2 (en) 2001-05-04 2010-10-12 Philip Morris Usa Inc. Apparatus and method for delaminating parcels of tobacco
CN104167379A (en) * 2013-05-17 2014-11-26 佳能安内华股份有限公司 Etching apparatus
CN110389607A (en) * 2018-04-23 2019-10-29 东京毅力科创株式会社 Temprature control method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030540U (en) * 1983-08-03 1985-03-01 株式会社日立製作所 Cooling device for wafer loading table
JPS63311726A (en) * 1987-06-15 1988-12-20 Ulvac Corp Microwave plasma processor
US4859304A (en) * 1988-07-18 1989-08-22 Micron Technology, Inc. Temperature controlled anode for plasma dry etchers for etching semiconductor
US7810506B2 (en) 2001-05-04 2010-10-12 Philip Morris Usa Inc. Apparatus and method for delaminating parcels of tobacco
WO2004093167A3 (en) * 2003-03-31 2005-06-09 Lam Res Corp Substrate support having temperature controlled surface
US7528073B2 (en) 2004-11-04 2009-05-05 Sumitomo Electric Industries, Ltd. Dry etching method and diffractive optical element
CN104167379A (en) * 2013-05-17 2014-11-26 佳能安内华股份有限公司 Etching apparatus
JP2014241394A (en) * 2013-05-17 2014-12-25 キヤノンアネルバ株式会社 Etching apparatus
US11195700B2 (en) 2013-05-17 2021-12-07 Canon Anelva Corporation Etching apparatus
CN110389607A (en) * 2018-04-23 2019-10-29 东京毅力科创株式会社 Temprature control method

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