JPS59170881A - Formation of electrode for liquid crystal panel - Google Patents

Formation of electrode for liquid crystal panel

Info

Publication number
JPS59170881A
JPS59170881A JP4521283A JP4521283A JPS59170881A JP S59170881 A JPS59170881 A JP S59170881A JP 4521283 A JP4521283 A JP 4521283A JP 4521283 A JP4521283 A JP 4521283A JP S59170881 A JPS59170881 A JP S59170881A
Authority
JP
Japan
Prior art keywords
electrode
crystal panel
liquid crystal
electrode layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4521283A
Other languages
Japanese (ja)
Inventor
小芝 昇平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP4521283A priority Critical patent/JPS59170881A/en
Publication of JPS59170881A publication Critical patent/JPS59170881A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は液晶パネルの電極形成方法に関するものであり
、2重マ) IJソックス晶パネルの電極形成に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming electrodes in a liquid crystal panel, and more particularly, to a method for forming electrodes in a double-layer IJ sock crystal panel.

多重マ) IJソックス晶パネル、特に2重マトリック
ス液晶ノぐネルはポケットテレビへの応用が提案すレる
など近年注目を集めている。
IJ sock crystal panels, especially double matrix liquid crystal panels, have been attracting attention in recent years, with applications proposed for pocket TVs.

第1図は従来提案されている2重マトリックス液晶パネ
ルの電極パターンの一部分を示したものである。このよ
うな液晶パネルをポケットテレビに用いるには開口率(
すなわぢ有効画面面積に対する画素電極面積の総和との
比)が大きいことが重要である。すなわち開口率が大き
いほどコントラストがよくなるので画質が向上し見安く
なる。
FIG. 1 shows a portion of the electrode pattern of a conventionally proposed dual matrix liquid crystal panel. In order to use such a liquid crystal panel in a pocket TV, the aperture ratio (
In other words, it is important that the ratio (the ratio of the total area of pixel electrodes to the effective screen area) be large. In other words, the larger the aperture ratio, the better the contrast, which improves the image quality and makes it easier to see.

このため、リード電極(例えば7)の幅はなるべく細く
、リード電極と画素電極の隙(たとえば7と2の隙)は
なるべく狭く、画素電極の隙(たとえば1と2の隙)も
なるべく狭く、リード電極間の隙(たとえば8と9の腋
)もなるべく狭くする必要がある。しがしながら、電極
の幅を細くするにつれ、あるいは間隙を狭くするにつれ
、電極のショートおよび断線の恐れが増大する。本発明
者の実験によれば、このような2重マトリックス液晶パ
ネルの電極形成を歩留りよく作成するには電極幅なtら
びにi+を極間隙を4oμ常以上とる必要がある。これ
Kより、リード電極幅を40 /J m 、電極間隙を
40μm1画素電極を30011mに設定すると開口率
は588%となりテレビ用に用いるには不十分な画質し
か得られなかった。
Therefore, the width of the lead electrode (for example, 7) is as narrow as possible, the gap between the lead electrode and the pixel electrode (for example, the gap between 7 and 2) is as narrow as possible, and the gap between the pixel electrodes (for example, the gap between 1 and 2) is as narrow as possible. It is also necessary to make the gap between the lead electrodes (for example, the armpits of 8 and 9) as narrow as possible. However, as the width of the electrode is made narrower or the gap is narrower, the risk of electrode shorting and disconnection increases. According to the experiments of the present inventors, in order to form electrodes of such a double matrix liquid crystal panel with a high yield, it is necessary to set the electrode width t and i+ so that the electrode gap is 4 μm or more. From this K, when the lead electrode width was set to 40/J m, the electrode gap was set to 40 μm, and one pixel electrode was set to 30,011 m, the aperture ratio was 588%, and an image quality insufficient for use in television was obtained.

本発明はこのような欠点を解消し、歩留りよくしかも開
口率の大きい2重マトリックス液晶パネル用電極の形成
方法を提供するものである。
The present invention eliminates these drawbacks and provides a method for forming electrodes for a double matrix liquid crystal panel with a high yield and a large aperture ratio.

第2図は本発明による2重マ) IJソックス晶パネル
用電極形成方法の一実施例を示した説明図である。以下
図面をもと((本発明の有効性について詳述する。
FIG. 2 is an explanatory view showing an embodiment of the method for forming electrodes for a double IJ sock crystal panel according to the present invention. The effectiveness of the present invention will be explained in detail below based on the drawings.

まず、第2図−(α)に示したごとく、ガラス基板1′
5上に透明導電膜14.Or膜i5.Au膜16.の順
に形成する。
First, as shown in Figure 2-(α), the glass substrate 1'
5, a transparent conductive film 14. Or film i5. Au film 16. Form in this order.

つぎに、第2図−(h)に示したごとく、電極基板ホト
レジストとホトマスクを用いてバターニングし、リード
電極(例えば17)ならびに画素電極(例えば20)と
なる部分を残してAu膜。
Next, as shown in FIG. 2-(h), patterning is performed using an electrode substrate photoresist and a photomask to form the Au film, leaving portions that will become lead electrodes (for example, 17) and pixel electrodes (for example, 20).

Cr膜、透明導電膜の順でエツチングする。Auのエツ
チング液にはヨードとヨー化カリとメタノールの混合水
溶液を用いた。また、(jrのエツチング液にはフェリ
シアン力りと水酸化カリの混合水溶液を用いた。さらに
、透明導電膜のエツチング液には塩酸を用いた。リード
電極(例えば17)の幅は40μ常、電極間隙(例えば
2oと21の隙)は10μmである。本考案者の実験に
よれば塵埃度クラス100の環境下でバターニングする
と23で示すような欠陥が単位面積当り約1ケ所の割合
で発生した。23はホコリ等によりホトレジストが取除
かれずに残り、下地の電極膜が残ったままになった部分
である。23の大きさは20〜50pm以下である。こ
の状態ではリード電極17と18はシロート状態にある
The Cr film and the transparent conductive film are etched in this order. A mixed aqueous solution of iodine, potassium iodide, and methanol was used as the Au etching solution. In addition, a mixed aqueous solution of ferrician and potassium hydroxide was used as the etching solution for (jr). Furthermore, hydrochloric acid was used as the etching solution for the transparent conductive film. The width of the lead electrode (for example, 17) is usually 40 μm. , the electrode gap (for example, the gap between 2o and 21) is 10 μm.According to the inventor's experiments, when patterning is performed in an environment with a dust level of class 100, defects as shown in 23 occur at a rate of about 1 per unit area. 23 is a part where the photoresist was not removed due to dust etc. and the underlying electrode film remained.The size of 23 is 20 to 50 pm or less.In this state, the lead electrode 17 and 18 are in the initial state.

つぎに1第2図−(c)に示すごとく、再度ホトレジス
トとホトマスク荀用いて第2図−Cb)と同一バターニ
ングをし、さらに再度Au膜。
Next, as shown in Fig. 2-(c), the same patterning as in Fig. 2-Cb) was performed again using photoresist and a photomask, and then the Au film was formed again.

Cr膜、透明導電膜の順でエツチングする。この結果、
同一位置の欠陥が生じる確率は〜0なので第2図−(5
)中にあった欠陥26は取除がnる。一方、新たな欠陥
としてピンボール24がやはり単位面積当り約1ケ所の
割合で発生する。しがし、ピンホールの大きさは20〜
30μ濯以下なのでリード電極19は断線することはな
い。
The Cr film and the transparent conductive film are etched in this order. As a result,
Since the probability of defects occurring at the same position is ~0, Figure 2-(5
) can be removed. On the other hand, as a new defect, pinballs 24 still occur at a rate of approximately one location per unit area. However, the size of the pinhole is 20~
Since the amount of rinsing is less than 30μ, the lead electrode 19 will not be disconnected.

つぎに、第2図−(d)に示すごとく、ホトレジストと
ホトマスクを用いてバターニングし、画素電極(例えば
20)上のAu膜、Cr膜をエツチングする。Auおよ
びOrのエツチング液では透明導電膜はエツチングされ
ないので透明導電膜で形成された画素電極(例えば20
)を得ることができる。リード電極は抵抗を減らすため
金属膜が用いられているがその幅は10μmあれば十分
なので、図中画素電極と接している部分のリード電極の
幅は10μ濯に減らしてあり、相対的に画素電極の面積
を広げることができる。
Next, as shown in FIG. 2-(d), patterning is performed using a photoresist and a photomask, and the Au film and Cr film on the pixel electrode (for example, 20) are etched. Since the transparent conductive film is not etched with Au and Or etching solutions, the pixel electrode formed of the transparent conductive film (for example, 20
) can be obtained. A metal film is used for the lead electrode to reduce resistance, but a width of 10 μm is sufficient, so the width of the lead electrode in the part in contact with the pixel electrode in the figure is reduced to 10 μm, so that the pixel The area of the electrode can be expanded.

このようにして構成された2重マトリックス液晶パネル
の開口率は798%となり従来に比べて開口率を大幅に
改善できるとともにテレビ用に用いても見栄えは格段に
よくすることができる。
The aperture ratio of the dual matrix liquid crystal panel constructed in this manner is 798%, which is a significant improvement over the conventional panel, and the appearance can be significantly improved even when used for television.

以上説明したごとく、本発明を用いるならば歩留りよく
しかも開口率の大きい2重マトリックス液晶パネルの形
成方法を提供することができる。
As described above, if the present invention is used, it is possible to provide a method for forming a double matrix liquid crystal panel with a high yield and a large aperture ratio.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来提案されている2重マ) IJソックス晶
パネルの電極パターンの一部分を示したものである。第
2図a、b、c、dは本発明による2重マトリックス液
晶パネル用電極形成方法の一実施例を示した説明図であ
る。 1.2,3,4,5.6・・・・・・画素電極7.8,
9,10・・・・・・リード電極11.12・・・・・
・外部接続端子 16・・・・・・ガラス基板 14・・・・・・透明導電膜 15・・・・・・Or膜 16・・・・・・Au膜 17.18,19  ・・・ ・・・ リ − ド11
を極2 ’(] 、 21 、22・・・・・・画素電
極23.24・・・・・・欠 陥 以  上 出願人 株式会社第二精工舎 代理5人 弁狐士 最上  務−、コ)。 千1図
FIG. 1 shows a portion of the electrode pattern of a conventionally proposed double IJ sock crystal panel. FIGS. 2a, b, c, and d are explanatory diagrams showing one embodiment of the method for forming electrodes for a double matrix liquid crystal panel according to the present invention. 1.2, 3, 4, 5.6...Pixel electrode 7.8,
9, 10...Lead electrode 11.12...
・External connection terminal 16...Glass substrate 14...Transparent conductive film 15...Or film 16...Au film 17, 18, 19...・・Lead 11
Pole 2'(], 21, 22... Pixel electrode 23, 24... Defects or more Applicant Daini Seikosha Co., Ltd. 5 representatives Benkosha Tsutomu Mogami-, Ko ). 1,000 figures

Claims (1)

【特許請求の範囲】 (1)第1のマスクで第1の電極層と第2の電極層をエ
ツチングし、次に第2のマスクで第1の電極層と第2の
電極層をエツチングし、次に第3のマスクで第1の電極
層をエツチングしたことを特徴とする液晶パネル用電極
形成方法。 (2)  ガラス基板上に第2の電極層が形成され、そ
の上に第1の1重極層が形成されていることを特徴とす
る特許請求の範囲第1項記載の液晶パネル用電極形成方
法。 (8)第1の電極層がAu膜とCjr膜で形成され、第
2の電極層が透明導電膜で形成されていることを特徴と
する特許請求の範囲第1項記載の液晶パネル用電極形成
方法。 (4)  第1の電極層をリード電極に用い、第2の電
極層を画素電極に用いたことを特徴とする特許請求の範
囲第1項記載の液晶パネル用電極形成方法。 (5)リード電極の幅が40μm以上であることを特徴
とする特許請求の範囲第1項記載の液晶パネル用電極形
成方法。 (6)  画素電極と接続するリード電極部分は第1の
電極層の幅が10μ脩以上、40μm以下でああことを
特徴とする特許請求の範囲第1項記載の液晶パネル用電
極形成方法。 (7)′電極間隙が1011m以上、40μ着以下であ
ることを特徴とする特許請求の範囲第1項記載の液晶パ
ネル用電極形成方法。
[Claims] (1) Etching the first electrode layer and the second electrode layer with the first mask, and then etching the first electrode layer and the second electrode layer with the second mask. . A method for forming electrodes for a liquid crystal panel, characterized in that the first electrode layer is then etched using a third mask. (2) Formation of an electrode for a liquid crystal panel according to claim 1, characterized in that a second electrode layer is formed on a glass substrate, and a first monopole layer is formed thereon. Method. (8) The electrode for a liquid crystal panel according to claim 1, wherein the first electrode layer is formed of an Au film and a CJR film, and the second electrode layer is formed of a transparent conductive film. Formation method. (4) The method for forming electrodes for a liquid crystal panel according to claim 1, wherein the first electrode layer is used as a lead electrode, and the second electrode layer is used as a pixel electrode. (5) The method for forming an electrode for a liquid crystal panel according to claim 1, wherein the width of the lead electrode is 40 μm or more. (6) The method for forming an electrode for a liquid crystal panel according to claim 1, wherein the width of the first electrode layer of the lead electrode portion connected to the pixel electrode is 10 μm or more and 40 μm or less. (7) The method for forming electrodes for a liquid crystal panel according to claim 1, wherein the electrode gap is 1011 m or more and 40 μm or less.
JP4521283A 1983-03-17 1983-03-17 Formation of electrode for liquid crystal panel Pending JPS59170881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4521283A JPS59170881A (en) 1983-03-17 1983-03-17 Formation of electrode for liquid crystal panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4521283A JPS59170881A (en) 1983-03-17 1983-03-17 Formation of electrode for liquid crystal panel

Publications (1)

Publication Number Publication Date
JPS59170881A true JPS59170881A (en) 1984-09-27

Family

ID=12712957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4521283A Pending JPS59170881A (en) 1983-03-17 1983-03-17 Formation of electrode for liquid crystal panel

Country Status (1)

Country Link
JP (1) JPS59170881A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501805A (en) * 1973-05-14 1975-01-09
JPS556346A (en) * 1978-06-27 1980-01-17 Sharp Kk Electrode pattern and method of forming same
JPS57161882A (en) * 1981-03-31 1982-10-05 Hitachi Ltd Display body panel
JPS57174808A (en) * 1981-04-17 1982-10-27 Sharp Kk Method of forming electrode pattern

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501805A (en) * 1973-05-14 1975-01-09
JPS556346A (en) * 1978-06-27 1980-01-17 Sharp Kk Electrode pattern and method of forming same
JPS57161882A (en) * 1981-03-31 1982-10-05 Hitachi Ltd Display body panel
JPS57174808A (en) * 1981-04-17 1982-10-27 Sharp Kk Method of forming electrode pattern

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