JPS59161049A - Multilayer interconnection member and manufacture thereof - Google Patents

Abstract

PURPOSE:To inhibit the generation of a crevasse stepped difference section, to improve the degree of connection between a lower wiring and an upper wiring and to enhance reliability by forming a protective film having an etching rate different from an insulating film between wirings on a first wiring. CONSTITUTION:An insulating film 2, a first wiring 5 and a protective film 6 are formed on a semiconductor substrate 1, and an insulating film 7, an etching rate thereof is slower than the protective film 6, is formed. A through-hole 9 is formed through etching according to specifications in which the etching rate of the insulating film 7 is slower than the protective film 6 by using a mask 8. The through-hole 9 is shaped in a self-alignment manner by the first wiring 5 without being affected by the displacement of the mask, and a crevasse stepped difference section is not also generated. A second wiring 10 is formed, and an insulating film 11 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a multilayer wiring member and a method of manufacturing the same.

2. Description of the Related Art In recent years, the degree of integration of semiconductor elements constituting a semiconductor device has been completely improved, and there has been an extremely strong tendency to use multilayer interconnections to connect them.

In the multilayer wiring of a semiconductor device, holes (hereinafter referred to as "through holes") for connecting the wirings are formed in an insulating film provided between the wirings, and the wirings are interconnected via the through holes. Therefore, the performance of the semiconductor device is influenced by how the through holes are formed.

In the manufacturing process of semiconductor devices,
In particular, variations in the thickness of the insulating film that should be provided between wirings are a major problem. This variation in the thickness of the insulating film is relatively large compared to the variation in the thickness of other parts such as wiring. Such variations in the thickness of the insulating film are caused by various factors in the formation of the insulating film, such that the film is generally thicker at the center of the semiconductor wafer than at the periphery.

Therefore, it is extremely difficult to uniformly form through-holes to be provided in the insulating film under the same conditions over the entire semiconductor wafer, which is one of the reasons for the occurrence of frebus step portions in some parts.

Another reason for the occurrence of the flare path step portion is the mask alignment (mask) between the mask for forming the through hole and the lower wiring when forming the through hole.
(alignment) may be caused by misalignment.

Due to this reason, it has been extremely difficult to attach the sub-wiring to the upper wiring which should be connected to the lower wiring via the through-hole due to the steep step difference in the flap pass portion.

This has the drawback of causing disconnection noise in the upper wiring at the stepped portion, impairing the reliability of the semiconductor device.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, suppress the occurrence of freckled step portions due to various causes, improve the degree of connection between the lower wiring and the upper wiring, and completely improve the reliability of the multilayer wiring member. It is in.

Furthermore, another object of the present invention is to suppress misalignment between the through hole and the lower wiring, and to improve the degree of integration of the multilayer wiring member.

Hereinafter, the present invention will be described in detail along with the - implementation sequence.

It should be noted that in all the figures, all signals having all the same functions are the same, and the explanation of their return will be omitted. In this embodiment, connection between wiring lines provided on a semiconductor substrate will be explained.

1 to 7 are sectional views of essential parts of a semiconductor device in each manufacturing process for explaining an embodiment of the present invention, and FIG. 8 is a sectional view taken along line XX in FIG. 7.

First, a P-type silicon single crystal semiconductor substrate 1 containing boron (B) impurities is prepared. On this substrate 1, an element region of a semiconductor element (circuit element) is formed in advance.

This semiconductor substrate 1 is subjected to heat treatment at about 1000°C, and as shown in FIG.
An insulating film 2 made of Sio2) is formed. This insulating film 2
is the semiconductor substrate 1-! It is designed to cover a semiconductor element (I7 not shown) whose shape is tightly fitted to the semiconductor substrate 1.

After the process shown in FIG. 1, a wiring material 3 that will become a lower wiring (hereinafter referred to as a first wiring) is formed on the entire surface. This wiring material 3 is made of, for example, aluminum (A4'),
Snow ivy evaporated gold is applied at about 0℃, the film thickness is 1.0μ
About m is sufficient. Thereafter, as shown in FIG. 2, a protective material 4 that becomes a protective film is entirely formed on the wiring material 3. This protective material 4 may be formed to a thickness of about 1.0 μm by, for example, nitride (SisN<)t: plasma deposition method.

Further, the wiring material 3 may be a metal with a high melting point such as silicon (sh') or molybdenum (MO), or a metal such as silicide which is a compound of a high melting point metal and silicon (hereinafter referred to as other wiring material). As the material 4, titanium tungsten (Tib), molybdenum (Mo'), etc. may be used. Note that the wiring material 3 and the protective material 4 are such that the wiring material 3 is not etched when the protective material 4 is etched, or the etching speed of the wiring material 3 is not significantly slower than the etching speed of the protective material 4. Must not be.

After the process shown in Figure 2, photoresist is applied to the entire surface. form,
In a later step, the photoresist is removed from areas other than those on which the first wiring layer is to be formed, thereby forming a single mask for etching resistance. Using this mask, as shown in FIG. 3, the stiffness-retaining material 4 and the wiring material 3 other than the lower part of the book are removed, and the entire wiring consisting of the first wiring 5 and the protective film 6 is formed. This uses a resist mask sound to dry
The etching tri can be formed by applying a wet etching layer. After this, the resist mask is completely removed.

After the step shown in FIG. 3, as shown in FIG. 4, an insulating film 7 of silicon dioxide is formed by, for example, Brehner type bias sputtering technique. The thickness of this insulating film 7 is 2
．． Approximately 5 μm is sufficient. This insulating film 7 may be a film that has a higher etching speed than the protective film 6 or a protective film 6.
An insulating film made of other tung metal may be used as long as the etching gas or solution that mainly etches the material is different from that used for etching. Ru. This is because the Brehner type bias sputtering technique deposits an insulating film, but at the same time generates a glow discharge in a vacuum, and the argon (Ar) gas introduced by the glow discharge is ionized, and the etching process is caused by the ions. It also acts. This etching effect is applied to the corners.

The deposition of the insulating film on the protruding portion is significantly reduced. Therefore, there is no protuberance of the insulating film 7 at the wiring portion consisting of the first wiring 5 and the protective film 6, and the entire surface becomes flat.

After the step shown in FIG. 4, the photoresist is completely removed from the entire surface, and as shown in FIG. form. The processing dimensions of this mask need only be larger by the allowable error dimension in consideration of the mask alignment misalignment between the mask 8 and the first wiring 5. This mask 8
Using etching specifications such that the etching speed of the insulating film 7 is slower than the etching speed of the d-holding film 6, the through holes 9 are formed. After this, mask 8
When completely removed, the result will be as shown in FIG. Through hole 9? For example, the etching process for forming
F) Dry etching of yarn may be used. For example, if the etching rate of the protective film 6 and the insulating film 7 is set to 2:1, when the insulating film 7 is etched by about 0.75 μm, the protective film 6 is etched and the upper surface of the first wiring 5 is exposed. It's like doing that.

As a result, the first wiring 5 and the through hole 9 are not affected by the misalignment of the mask for forming the through hole 9, and the through hole 9 is formed by the first wiring 5 with self-alignment. be done. Furthermore, there is no possibility of noise occurring at the step part of the frebass.

After the process shown in FIG. 6, the first
An upper wiring (hereinafter referred to as the "second wiring") 10"k is formed to connect with the wiring 5, and as shown in FIG.
An insulating film 11 made of phosphor silicate glass (PSG) is formed on top of the substrate 0 . The second wiring 10 is made of aluminum or other wiring material, and has a film thickness of 1.0 μm.
It is enough.

The insulating film 11 has functions such as protecting the semiconductor device and mitigating protrusions and protrusions caused by multilayer wiring, and may have a thickness of about 8000 Å.

FIG. 8 is a sectional view taken along line XX in FIG. 7.

Through these series of steps, the semiconductor device of this example is completed.

FIG. 9 is a sectional view of a main part of a semiconductor device in one manufacturing process for explaining another embodiment of the present invention. In this embodiment, a case will be explained in which all the through holes are formed by another etching process using the Hiko mask 8 as shown in FIG. 5 of the previous embodiment.

After the step shown in FIG. 5 of the manufacturing method of the embodiment, wet etching is applied to the insulating film 7 using a mask 8 so that the upper surface of the protective film 6 is exposed.

At this time, etching is performed such that the protective film 6 is hardly etched. After that, the insulating film 7 is hardly etched and the protective film 6 is entirely removed by dry etching, so that the upper surface of the first wiring 5 is exposed, as shown in FIG. , through hole 1
2'. The wet etching of the insulating film 7 may be dry etching in which the protective film 6 is hardly etched.

After the process shown in FIG. 9, the semiconductor device of this example is completed by using the process shown in FIG. 7 of the manufacturing method of the above-mentioned example.

Next, the present invention will be explained in detail.

Figure 10 (A), (B) and Figure 11 (A), (B
) are sectional views of main parts in each manufacturing process of a semiconductor device for explaining application examples of the present invention. This application example is a case where there is variation in the thickness of the insulating film between each wiring, and will be explained using one embodiment of the present invention. In addition, Fig. 10 (
4), FIG. 11(4) shows the wiring portion with the maximum thickness of the insulating film with variations in film thickness, and FIG. 10(1)).

FIG. 11(B) shows a wiring portion with a small thickness of an insulating film with variations in film thickness. Furthermore, variations in the thickness of the wiring, protective film, etc. are extremely small compared to variations in the thickness of the insulating film, so they are ignored in this application example.

After the step shown in FIG. 3 of the manufacturing method of the embodiment, as shown in FIG. 10, an insulating film 7 of silicon dioxide is formed by Brehner type bias sputtering technique. However, variations in the thickness of the insulating film 7 occur due to various factors. As a result, an insulating film 7A with the maximum thickness as shown in FIG. 10(IA) and an insulating film 7B with the minimum thickness as shown in FIG. 10(B) are formed. This insulating film 7A
The difference in film thickness between the insulating film 7B and the insulating film 7B is Δt. This film thickness difference △t
can be predicted in advance, so the thickness of the protective film 6 formed in the previous step is controlled as shown in the following equation.

(Thickness of protective film 6) ≧ (i thickness difference Δt) Is there a through hole in the process shown in Figure 10? Mask all insulating film 7A for etching-resistant holes to be formed.

Form on 7B. Using all layers of this mask, the insulating films 7A and 7B are etched by dry etching so that the protective film 6 is not etched.

As a result, the upper portions of the first wiring 5 at the maximum and minimum thickness portions are exposed. Next, the protective film 6' is selectively removed by dry etching such that the insulating films 7A and 7B are not etched away. As a result, the upper surface portion of the first wiring 5 is exposed (Fig. 11).

As shown in CB), through holes 9A and 9B are formed a.

After the step shown in FIG. 11, the steps shown in FIG. 7 of the above embodiment are performed to complete the semiconductor device of this application example. As a result, the present invention can be applied even when the thickness of the insulating film between each wiring is uneven.

Normally, the etching control in the depth direction of the insulating films 7A and 7B is determined using the maximum thickness of the insulating film 78 as a reference. For this reason, conventionally, in the minimum thickness portion, a through hole deeper than the upper surface of the first wiring is formed (overetching), resulting in a frebas step portion fc. However, by applying the present invention, there is a margin in the thickness of the protective film 6 for etching control in the depth direction, so that no sound is generated at the stepped portion of the flexure. In addition, the protective film 6 protects the first
Because the through-hole can be formed by self-alignment with the wiring, there is no risk of misalignment between the first wiring and the through-hole formation, resulting in a visible repass step. It never happens and it goes away.

However, the first wiring 5 is hardly immersed in etching. Also, a wiring material that cannot be immersed may be used.

Next, all other application examples of the present invention will be explained.

FIGS. 12 and 13 are sectional views of main parts in each manufacturing process of a semiconductor device for explaining another application example of the present invention. This application example is a case where interconnections of different layers are connected, and will be explained using the above-mentioned embodiment.

In FIG. 12, an insulating film 7 is formed by a planar type insulating scattering technique on a wiring section consisting of first wirings 5A, 5B and a protective film 6A formed in the same layer on a semiconductor substrate 1 via an insulating film 2. has been done. Thereafter, a wiring layer consisting of a second wiring 5C and a protective film 6B is formed on the first wiring 5B. The thickness of the protective film 6B may be determined by the difference between the thickness of the insulating film 7 and the thickness of the wiring times the etch rate of the protective films 6A and 6B. And OV D ((3hetnica'l
An insulating film 11Ak is formed by a vapor dep-osltlon method.

This insulation 1411A may be used on phosphor silicate glass.

After the process shown in FIG. 12, the first wiring 5A and the second wiring 5
A through hole for connection with 0 is formed and a mask for etching resistance is completely formed. Using this mask, the insulating film 11A and the insulating film are etched by dry etching in a manner that prevents the protective films 6A and B from being etched, so that the upper portions of the protective films 6A and B that connect with the first wiring 5A and the second wiring 5C are exposed. Etching syllables on the insulating film 7 with 11A. Protective film 6
After the upper parts of A and B are exposed, the insulating film 7 and the insulating film 1 are
The protective films 6A and 6B are selectively etched 111- by dry etching such that the etching layer 1A is not etched.
The upper surface portions of the first wiring 5A and the second wiring 5C are exposed, and a null hole 9c9Di is formed. After this,
The third wiring 13 is formed so as to be connected to the first wiring 5A and the second wiring 5C via the through holes 9C and 9D. After that, an insulating film 11Bt made of phosphosilicate glass is formed on the entire surface by the OVD method, and the 13th
The result will be as shown in the figure.

Through these series of steps, the semiconductor device of this application example is completed.

This allows the total thickness of the different insulating films to be absorbed by the thickness of the protective film formed on the wiring, thereby making it possible to connect wirings in different layers in a multilayer wiring.

Of course, the present invention is not limited to the embodiments and application examples described above, and can be modified in various ways within the scope of the invention. For example, although the above embodiment describes the formation of a through hole, it may also be used as a contact hole for connecting a semiconductor head formed on a semiconductor substrate and wiring on the semiconductor substrate.

As explained above, according to the present invention, the first wiring and the second wiring
A through hole to be provided in the insulating film between the wirings for connection with the wiring is etched by a protective film that is etched at a different etching rate or with a different etching gas or solution than the insulating film provided on the first wiring, A through hole is formed in self-alignment with the first wiring. Also,
The depth direction of the through hole can be controlled by the protective film provided on the first wiring, which allows for a margin corresponding to the film thickness. 'Therefore, even if a through hole is formed in the insulating film between the first wiring and the second wiring for the purpose of connection between the wiring, no frebus step portion is generated, and the connection between the wirings is good. . Furthermore, the connection between the first wiring and the second wiring is good without producing a step portion due to a deviation between the first wiring and a mask for forming a through hole. This makes it possible to improve the reliability of multilayer wiring in semiconductor devices and the like.

Furthermore, by improving the reliability of multilayer wiring, the degree of integration at the corners of the semiconductor device can be completely improved.

[Brief explanation of drawings]

1 to 7 are sectional views of essential parts of a semiconductor device in each manufacturing process for explaining one embodiment 0 of the present invention; FIG. 8 is a sectional view taken along line XX in FIG. 7; FIG. 9 is a sectional view of a main part of a semiconductor device in one manufacturing process for explaining another embodiment of the present invention, and FIG. 10 (A'l,
(B''l and FIGS. 11(A) and 11) are cross-sectional views of essential parts in each manufacturing process of the k-th semiconductor device to be explained, and FIGS. The figure is a sectional view of a main part in each manufacturing process of a semiconductor device for explaining another application example of the present invention. In the figure, 1... semiconductor substrate, 2, 7, 7A, 7B. 11, IIA , IIB...insulating film, 3...
Wiring material, 4... Protective material, 5.5A, 5B... First wiring, 6... Protective film, 8 Mask, 9, . 9A,
9B, 90.9D. 12・Through hole, 10...Second wiring, 13...
This is the third wiring. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure J Figure 8 Figure 9 Inside Hitachi, Ltd. Device Development Center, 1450 Josui Honmachi, Kodaira City ■Applicant Corporation Hitachi, Ltd. No. 1-5 Marunouchi-chome, Chiyoda-ku, Tokyo Written amendment (method) Case description 1982 Patent Application No. 34598 Name of the invention Multilayer wiring member and its manufacturing method Person who makes the amendment 1.t't No. 1 Patent applicant name: '51Ql:I: y(kai)t
Page 18, line 1 of the amendment to the brief explanation of the drawings in the Hitachi Manufacturing Specification [Figure 10 (4), (B)
10”.

Claims (1)

[Scope of Claims] 1. In a multilayer wiring member in which insulating films and wiring layers are alternately formed in multiple layers, at least two wirings in a first layer provided in different interconnection areas on the insulating film; A second layer of wiring is provided on one of the wirings via an insulating Mk, and a first layer of wiring is provided on an insulating film above the other wiring of the first layer.
and a second connection hole provided in the insulating film above the second-layer wiring, and the first and second wirings are connected so as to fully connect the other wiring and the second-layer wiring. A multilayer wiring member comprising a third layer of wiring provided through two connection holes. 2. A step of forming a first insulating film on the substrate, a step of forming a first wiring on top of the first insulating film, a step of forming a wiring made of a six-year insurance film on top of the first wiring, and forming a second insulating film on the entire surface. forming a connection hole by removing the second insulating film above the wiring and the protective film above the first wiring; forming the second wiring so as to connect to the first wiring through the connection hole; 1. A method for manufacturing a multilayer wiring member, comprising a step of forming. 3. The method of manufacturing a multilayer wiring member according to claim 2, wherein the step of forming all the contact holes takes full advantage of the fact that the protective film and the second insulating film have different etching rates. A method for manufacturing a multilayer wiring member, characterized in that: 4t ¥! f) The method for manufacturing a multilayer wiring member according to claim 2, wherein the step of forming the connection hole includes etching the second insulating film so that the protective film is not etched; A method for manufacturing a multilayer wiring member, characterized in that the protective film is formed by etching the entire protective film so that it is not etched.