JPS59148430A - Logical operating circuit - Google Patents

Logical operating circuit

Info

Publication number
JPS59148430A
JPS59148430A JP58021680A JP2168083A JPS59148430A JP S59148430 A JPS59148430 A JP S59148430A JP 58021680 A JP58021680 A JP 58021680A JP 2168083 A JP2168083 A JP 2168083A JP S59148430 A JPS59148430 A JP S59148430A
Authority
JP
Japan
Prior art keywords
power supply
circuit
switch
tri
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58021680A
Other languages
Japanese (ja)
Inventor
Tetsushiro Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58021680A priority Critical patent/JPS59148430A/en
Publication of JPS59148430A publication Critical patent/JPS59148430A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent an adverse effect on a corresponding element or the operation of the entire logical operating element by inserting a buffer circuit between a common signal line and the element whose power supply is interrupted.
CONSTITUTION: When a switch SW1 is opened to interrupt the power supply to a device 33, a switch SW2 is opened in interlocking with the switch SW1 and an output of a tri-state buffer circuit 4 has high impedance (the circuit 4 performs a normal buffer operation at a VSS potential and becomes tri-state at a VCC potential). Thus, the common signal line 1 and the device 33 are separated by this tri-state buffer circuit 4, and since the output of the said circuit 4 is connected to a power supply terminal P3 of the device 33 via resistors R1∼R8, the potential of the input and the power supply side is made equal.
COPYRIGHT: (C)1984,JPO&Japio
JP58021680A 1983-02-14 1983-02-14 Logical operating circuit Pending JPS59148430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58021680A JPS59148430A (en) 1983-02-14 1983-02-14 Logical operating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58021680A JPS59148430A (en) 1983-02-14 1983-02-14 Logical operating circuit

Publications (1)

Publication Number Publication Date
JPS59148430A true JPS59148430A (en) 1984-08-25

Family

ID=12061772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58021680A Pending JPS59148430A (en) 1983-02-14 1983-02-14 Logical operating circuit

Country Status (1)

Country Link
JP (1) JPS59148430A (en)

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