JPS59139656A - High dielectric strength resin package type semiconductor device - Google Patents
High dielectric strength resin package type semiconductor deviceInfo
- Publication number
- JPS59139656A JPS59139656A JP1271683A JP1271683A JPS59139656A JP S59139656 A JPS59139656 A JP S59139656A JP 1271683 A JP1271683 A JP 1271683A JP 1271683 A JP1271683 A JP 1271683A JP S59139656 A JPS59139656 A JP S59139656A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- header
- mounting
- resin package
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高耐圧レジンパッケージ型半導体装置、たとえ
ば高耐圧レジンパワートランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage resin packaged semiconductor device, such as a high voltage resin power transistor.
レジンパッケージ型パワートランジスタ（レジンパワー
トランジスタ）は、第１図で示すように、チップ５が主
面で固定さねているヘッダ１０をマイカ板１を介して放
熱板２に絶縁的に取り付け、ビスを用いて固定する構造
を有する。このためビス３を挿入する取付用孔４はチッ
プ５を固定するへ・ラダ６と、このヘッダ６の主面にチ
ップ５を被うように設けられるレジンパッケージ７とを
貫通するように設けられている。また、ヘッダ６とビス
３との絶縁性を維持させるために、へ・ラダ６には取付
用孔４と同心円となる孔８をヘッダ６に設け、レジンパ
ッケージングの際にこの孔８と取付用孔４との間にドー
ナツ状にレジンｋＨし込んで耐圧維持層９を設けている
。なお、図中１０はリード、１１はリード１０の内端と
チップ５の電極とを接続する導電性のワイヤ、１２はビ
ス３に螺合されてパワートランジスタ１３を放熱板２に
固定するナンドである。As shown in FIG. 1, a resin packaged power transistor (resin power transistor) is constructed by insulatingly attaching a header 10, on which a chip 5 is fixed on its main surface, to a heat sink 2 via a mica plate 1. It has a structure that is fixed using. Therefore, the mounting hole 4 into which the screw 3 is inserted is provided so as to pass through the ladder 6 for fixing the chip 5 and the resin package 7 provided on the main surface of the header 6 so as to cover the chip 5. ing. In addition, in order to maintain the insulation between the header 6 and the screws 3, a hole 8 that is concentric with the mounting hole 4 is provided in the header 6, and the hole 8 and the mounting hole 8 are provided in the header 6 during resin packaging. A pressure-resistant maintenance layer 9 is provided by injecting resin kHz into the hole 4 in a donut shape. In the figure, 10 is a lead, 11 is a conductive wire that connects the inner end of the lead 10 and the electrode of the chip 5, and 12 is a NAND that is screwed into the screw 3 to fix the power transistor 13 to the heat sink 2. be.
しかし、このような構造では耐圧に問題があることがわ
かった。すなわち、前記耐圧維持層９の厚さはパワート
ランジスタ１３の耐圧値に対応して決定されるので本来
は耐圧不良は生じない筈である。しかし、第２図に水子
ように、ミクロ的に観察すれば孔８の縁部分は凹凸が激
しい。また、この孔８けプレスによって打ち抜いて形成
される。However, it has been found that such a structure has a problem with voltage resistance. That is, since the thickness of the breakdown voltage maintenance layer 9 is determined in accordance with the breakdown voltage value of the power transistor 13, a breakdown voltage failure should not occur. However, as shown in FIG. 2, when observed microscopically, the edges of the holes 8 are extremely uneven. Further, it is formed by punching with this 8-hole press.
このため、打ち抜きばシと呼ぶ長い突起１４も孔８の周
縁部に存在し、実際の絶縁間隔ｌは設計値りよシも短か
くなってしまう。また、これら突起先端部では電界集中
が生じて放電、し易くなシ耐圧の低下を来たしてしまう
。For this reason, a long protrusion 14 called a punching hole is also present at the periphery of the hole 8, and the actual insulation interval l is shorter than the design value. In addition, electric field concentration occurs at the tips of these protrusions, making it easy to discharge and lowering the withstand voltage.
一方、このような耐圧似下防止のために、ヘッダ６に設
ける孔８の内径を大きくする構造もあるが、孔８ｆ：大
きくするとヘッダ６に取シ付けることのできるチップ５
の大きさも小さくなっタリ、あるいけパワートランジス
タ１３０寸法が大型化する不都合が生じる。On the other hand, there is a structure in which the inner diameter of the hole 8 provided in the header 6 is increased in order to prevent such a drop in withstand pressure.
As a result, the size of the power transistor 130 becomes smaller, resulting in an inconvenience that the dimensions of the power transistor 130 become larger.
したがって、本発明の目的は取付用孔の寸法を変えるこ
となく耐圧性を高めることができる高耐圧レジンパッケ
ージ型半導体装置を提供することにある。Therefore, an object of the present invention is to provide a high-voltage resin-packaged semiconductor device that can improve pressure resistance without changing the dimensions of the mounting hole.
以下、実施例によシ本発明を説明する。The present invention will be explained below with reference to Examples.
第３図は本発明の一実施しＩ］による高耐圧レジンパワ
ートランジスタを示す断面図、第４図は第３図のＩＶ−
Ｔｌ／線に沿う断面図である。FIG. 3 is a cross-sectional view showing a high voltage resin power transistor according to one embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along the Tl/ line.
パワートランジスタ１３は金属製ヘッダ６と、このヘッ
ダ６の主面に取ｐ付けたチップ５と、このヘッダ６の主
面に設けられ前記チップ５を被うレジンからなるレジン
パッケージ７と、ヘッダ６の一端から延在する１本のリ
ード１０およびこのリード１０の両側にそれぞれ平行と
なって延在する１本ずつのリード１０と、前記両側のリ
ード１０の内端とチップ５の電極とを接続する導電性の
ワイヤ１１と、からなっている。前言己リード１０の外
端はレジンパッケージ７から突出し、その突出部は接続
端子となっている。また、レジンパッケージ７はヘッダ
６の主面側に設けられることからヘッダ６から剥離し易
い。そこで、第４図に示すように、ヘッダ６の側面には
コイニングによって形成される突起１５が設けられ、レ
ジンパッケージ７の一部がこの突起１５に喰い込んで剥
離し難いようになっている。The power transistor 13 includes a metal header 6, a chip 5 attached to the main surface of the header 6, a resin package 7 made of resin provided on the main surface of the header 6 and covering the chip 5, and the header 6. One lead 10 extending from one end and one lead 10 extending parallel to each side of this lead 10, and the inner ends of the leads 10 on both sides and the electrodes of the chip 5 are connected. It consists of a conductive wire 11. The outer end of the lead 10 protrudes from the resin package 7, and the protruding portion serves as a connection terminal. Further, since the resin package 7 is provided on the main surface side of the header 6, it is easily peeled off from the header 6. Therefore, as shown in FIG. 4, a protrusion 15 formed by coining is provided on the side surface of the header 6, so that a portion of the resin package 7 is bitten into the protrusion 15 and is difficult to separate.
一方、このパワートランジスタ１３には放熱板１２にマ
イカ枦１を介して絶縁的に取９個ける除用いるビス３挿
入用の取付用孔４が設けられている。この取付用孔４は
レジンパッケージ７おまひヘッダ６を貫通している。ま
た、ヘッダ６の取付用孔部分には取付用孔４よりも直径
が大きい孔８が同心円的に設けられている。この孔８は
ヘッダ６の主面とは逆となる取付面側ではさらにその直
径が大きな安全孔１６となっている。この安全孔１６は
後述する耐圧維持層のレジンが割れて脱落しないための
埋さが必要なことから０．５ｍｍ程度の深さでかつ孔８
よシけ４ｍｍ程度大きくなっていて、たとえばコイニン
グによって形成される。そして、孔８および安全孔１６
と取付用孔４との間はレジンパッケージ形成時のモール
ドにおいてレジンで埋められて耐圧維持層９となる。ま
た、孔８と取付用孔４に亘る部分の耐圧維持層９の厚さ
はたとえば１〜１５聴となシ、約１８００〜２００Ｑｖ
の高耐圧にも充分耐えるようになっている。On the other hand, in the power transistor 13, a mounting hole 4 for inserting nine screws 3, which can be removed insulatively, is provided in the heat sink 12 through a mica shell 1. This mounting hole 4 passes through the resin package 7 and the header 6. Further, a hole 8 having a diameter larger than that of the mounting hole 4 is provided concentrically in the mounting hole portion of the header 6. This hole 8 becomes a safety hole 16 with a larger diameter on the mounting surface side opposite to the main surface of the header 6. This safety hole 16 needs to be filled to prevent the resin of the pressure-resistant maintenance layer from cracking and falling off, which will be described later.
The recess is about 4 mm larger and is formed, for example, by coining. And hole 8 and safety hole 16
The space between the mounting hole 4 and the mounting hole 4 is filled with resin to form a pressure-resistant maintaining layer 9 in a mold when forming a resin package. Further, the thickness of the pressure-resistant maintenance layer 9 in the portion extending between the hole 8 and the mounting hole 4 is, for example, 1 to 15 Qv, and approximately 1800 to 200 Qv.
It is designed to withstand high pressure resistance.
このようなパワートランジスタ１３はその実装におって
は、放熱板２上にマイカ板１を介して載置され、ビス３
およびナヴト１２によって固定される。In mounting, such a power transistor 13 is placed on a heat sink 2 with a mica plate 1 in between, and screws 3
and fixed by Navut 12.
コノパワートランジスタ１３はその取付面側ではビス３
とヘッダ縁との間隔ａは孔８とビス３との間隔りよシも
広くなる。この結果、ビシ３とヘッダ６との縁面距離は
従来品よシも長くなることから、耐圧は高くなる。した
がって、１８００〜２０００Ｖと極めて高耐圧を保証す
るパワートランジスタにおいても、耐圧不良は生じなく
なる。The cono power transistor 13 has screws 3 on its mounting surface side.
The distance a between the hole 8 and the header edge is also wider than the distance between the hole 8 and the screw 3. As a result, the edge distance between the bridge 3 and the header 6 is longer than that of the conventional product, so that the withstand voltage is increased. Therefore, even in a power transistor that guarantees an extremely high breakdown voltage of 1800 to 2000V, breakdown voltage failures will not occur.
着た、この実施例では、安全孔１６に入シ込んだ耐圧維
持層９部分が孔８を構成するヘッダ部分に引っ掛るため
、レジンパッケージ７がへラダ６゛から剥離し難くなシ
、耐滞性の向上も図れる。In this embodiment, the part of the pressure-resistant maintenance layer 9 that has entered the safety hole 16 is caught on the header part that constitutes the hole 8, so that the resin package 7 is not easily peeled off from the header 6'. It can also improve retention.
なお、本発明は前記実施例に限定されない。たとえば、
第５図に示すように、安全孔１６は孔８の縁部分をコイ
ニングによって埋し潰し、円錐状孔としてもよい。この
構造も前記実施例と同様に１高耐圧を維持でき、かつ耐
湿性の向上も図ることができる。Note that the present invention is not limited to the above embodiments. for example,
As shown in FIG. 5, the safety hole 16 may be formed by filling the edge of the hole 8 with coining to form a conical hole. This structure can also maintain a high withstand voltage as in the above embodiment, and can also improve moisture resistance.
本発明はトランジスタ以外の他の電子部品にも適用でき
る。The present invention can also be applied to electronic components other than transistors.
以上のように、本発明によれば実装時に用いる取付用孔
を変化させることなく高耐圧を給持できる耐湿性の優れ
た高耐圧レジンバ・ンケージ型半導体装置を提供するこ
とができる。As described above, according to the present invention, it is possible to provide a high voltage resin cage type semiconductor device with excellent moisture resistance and which can supply a high voltage resistance without changing the mounting holes used during mounting.
第１図は従来のパワートランジスタを示す断面図、
第２図は同じく耐圧不良状態を示す一部の断面図、
第３図は本発明の一実施例によるパワートランジスタの
断面図、
第４図は第３図の■−ｔｖｔｗに沿う断面図、第５図は
本発明の他の実施例によるパワートランジスタの断面図
である。
１・・・マイカ板、２・・・放熱板、３・・・ピヌ、４
・・・取付用孔、５・・・チップ、６・・・へ・ンダ、
７・・・レジンパッケージ、８・・・孔、９・・・耐圧
維持層、１２・・・ナツト、１３・・・パワートランジ
スタ、１４・・・打ち抜きばυ、１６・・・安全孔。FIG. 1 is a cross-sectional view showing a conventional power transistor, FIG. 2 is a partial cross-sectional view similarly showing a breakdown voltage failure state, FIG. 3 is a cross-sectional view of a power transistor according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a power transistor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along the line {circle around (2)-tvtw}, and FIG. 5 is a cross-sectional view of a power transistor according to another embodiment of the present invention. 1... Mica board, 2... Heat sink, 3... Pinu, 4
...Mounting hole, 5...Chip, 6...To/under,
7... Resin package, 8... Hole, 9... Withstand voltage maintenance layer, 12... Nut, 13... Power transistor, 14... Punching υ, 16... Safety hole.
Claims (1)
ジと、このレジンパッケージで被われかつヘッダの主面
に取シ伺けられたチップと、前記レジンパッケージとヘ
ッダとを貫通して設けられた取付用孔と、を有し、前記
ヘッダには取付用孔と同心円となる孔が設けられ、この
孔と取付用孔との間はレジンからなる耐圧維持層で埋め
られている高耐圧レジンパッケージ型半導体装置におい
て、前記ヘッダに設けられた孔の主面とは逆となる裏面
部分では孔の内径が他の部分よシも大きくなっているこ
とを特徴とする高耐圧レジンノンケージ型半導体装置。(2) A header, a resin package covering the main surface of the header, a chip covered by the resin package and mounted on the main surface of the header, and a chip provided passing through the resin package and the header. The header has a hole that is concentric with the mounting hole, and the space between the hole and the mounting hole is filled with a pressure-resistant maintenance layer made of resin. A high-voltage resin non-cage type semiconductor device in a packaged semiconductor device, characterized in that the inner diameter of the hole is larger on the back side opposite to the main surface of the hole provided in the header than on other parts. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1271683A JPS59139656A (en) | 1983-01-31 | 1983-01-31 | High dielectric strength resin package type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1271683A JPS59139656A (en) | 1983-01-31 | 1983-01-31 | High dielectric strength resin package type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59139656A true JPS59139656A (en) | 1984-08-10 |
Family
ID=11813151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1271683A Pending JPS59139656A (en) | 1983-01-31 | 1983-01-31 | High dielectric strength resin package type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59139656A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258622B2 (en) * | 2007-02-28 | 2012-09-04 | Fairchild Korea Semiconductor, Ltd. | Power device package and semiconductor package mold for fabricating the same |
-
1983
- 1983-01-31 JP JP1271683A patent/JPS59139656A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8258622B2 (en) * | 2007-02-28 | 2012-09-04 | Fairchild Korea Semiconductor, Ltd. | Power device package and semiconductor package mold for fabricating the same |
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