JPS5913326A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5913326A
JPS5913326A JP57123331A JP12333182A JPS5913326A JP S5913326 A JPS5913326 A JP S5913326A JP 57123331 A JP57123331 A JP 57123331A JP 12333182 A JP12333182 A JP 12333182A JP S5913326 A JPS5913326 A JP S5913326A
Authority
JP
Japan
Prior art keywords
pattern
oxide film
diffusion
impurity
water
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57123331A
Other languages
Japanese (ja)
Inventor
Mutsumi Matsuo
睦 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP57123331A priority Critical patent/JPS5913326A/en
Publication of JPS5913326A publication Critical patent/JPS5913326A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To permit a subsequent lithography process to be carried out successively, by regenerating a pattern on the semiconductor surface which has once disappeared in a diffusion pretreatment process or the like. CONSTITUTION:After a lithography process, an n type impurity 8 is doped by means of an ion implantation device or the like. If an oxide film is over-etched in a subsequent process of pretreatment for impurity diffusion, a pattern on the silicon surface becomes difficult or unable to observe. When the impurity 8 is thermally diffused, the pattern on the silicon surface becomes substantially unobservable. Therefore, the oxide film grown through the thermal diffusion is removed by etching the whole surface by means of hydrofluoric acid diluted with water. Then, a chemical etching is carried out with a hydrofluoric-nitric acid solution obtained by mixing a small amount of nitric acid into hydrofluoric acid diluted with water. After the impurity diffusion, the pattern is faintly observable. Even when the pattern becomes unobservable after the formation of the thermal oxide film, it becomes possible to effect a subsequent lithography process by removing the oxide film from the whole surface, carrying out the chemical etching, effecting a hot water cleaning treatment with an ammonia water and a hydrogen peroxide solution, and forming a thermal oxide film again.

Description

【発明の詳細な説明】 本発明は、半導体面上に、紫外線などに敏感な感光性高
分子材料(以下レジストと略す)を塗布し、その上に所
銀のパターンのマスクを重ねて紫外線などを照射した後
、レジストを現像し、そのレジストをマスクとして、エ
ツチングを行なう工程(以下リングラフィ工程と略すン
と次のリングラフィ工程の中間工程で、半導体面上の既
存のパターンが消えて見えなくなった場合において、既
存したパターンを見えるように再生して、次のリングラ
フィ工程を可能にする半導体装置の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention involves coating a semiconductor surface with a photosensitive polymer material (hereinafter referred to as resist) that is sensitive to ultraviolet rays, etc., overlaying a mask with a silver pattern on top of the photosensitive polymer material (hereinafter referred to as resist), After irradiating the resist, the resist is developed, and the resist is used as a mask to perform etching (hereinafter referred to as phosphorography process).In the intermediate process of the next phosphorography process, the existing pattern on the semiconductor surface disappears and becomes visible. The present invention relates to a method for manufacturing a semiconductor device that allows the existing pattern to be visibly reproduced to enable the next phosphorography process when the existing pattern is lost.

従来、半導体装置(たとえばトランジスタや集積回路な
ど)を製造するには、基板の一部へ局部的に不純物を拡
散したり、局部的に酸化したりするなどの必要があり、
これらの微細加工は、リングラフィ技術によって行なわ
れる。たとえばル型またはP型のシリコン基板上に部分
的に不純物を拡散したい場合、第1図に示すような工程
を行なう。まず高温酸素中でル型又はP型のシリコンウ
ェハー2を熱酸化し、ウェハ−2全面に酸化膜1を形成
する。この酸化膜1の上にレジスト3を塗布し、ガラス
基板4上のマスクパターン5を通して紫外線6により露
光する。その後の現像処理によってレジスト3が局部的
に溶解除去され、エツチング液のふり酸に浸すとレジス
ト膜3のない部分の酸化膜1のみがエツチングされ、レ
ジスト3を現像除去すれば必要な酸化膜1のパターンが
形成される。このようなリングラフィ工程から得られた
酸化膜1の窓を通して、必要な部分のみへの不純物拡散
を行ない不純物拡散層7を形成する。
Conventionally, in order to manufacture semiconductor devices (for example, transistors and integrated circuits), it is necessary to locally diffuse impurities into a part of the substrate or locally oxidize it.
These microfabrications are performed using phosphorography technology. For example, when it is desired to partially diffuse impurities onto a silicon substrate of a type or P type, a process as shown in FIG. 1 is performed. First, a R-type or P-type silicon wafer 2 is thermally oxidized in high-temperature oxygen to form an oxide film 1 on the entire surface of the wafer 2. A resist 3 is applied onto this oxide film 1 and exposed to ultraviolet rays 6 through a mask pattern 5 on a glass substrate 4. The resist 3 is locally dissolved and removed by the subsequent development process, and when immersed in fluoric acid, which is an etching solution, only the part of the oxide film 1 where there is no resist film 3 is etched. A pattern is formed. Through the window of the oxide film 1 obtained by such a phosphorography step, impurities are diffused only into necessary portions to form an impurity diffusion layer 7.

次にウェハー憂熱酸化して、全面酸化膜1を形成したの
ち、次のリングラフィ工程に移行する。ところが−途中
の不純物ドーピングあるいは不純物拡散の前処理工程で
の酸化膜エツチングなどの過剰によりパターンが見えに
くくなったりひどいときには全熱みえなくなったりする
ことがある。また熱拡散後にはうつすらと見えていても
、酸化膜形成後に見えなくなってしまうことがある。し
たがって、次のリングラフィ工程では、マスクとの位置
決めをしているシリコンウェハー上のマーカーが見えな
いために、マスク合せができないことになる。このよう
なときは、その半導体を工程中に大ていはすててしまう
Next, the wafer is thermally oxidized to form an oxide film 1 on the entire surface, and then the next phosphorography process is started. However, due to impurity doping during the process or excessive oxide film etching in the pretreatment process for impurity diffusion, the pattern may become difficult to see, or in severe cases, the total heat may not be visible. Furthermore, even if it appears blank after thermal diffusion, it may become invisible after the oxide film is formed. Therefore, in the next phosphorography process, the markers on the silicon wafer that are positioned with the mask cannot be seen, so mask alignment cannot be performed. In such cases, the semiconductor is often thrown away during the process.

本発明はかかる欠点を除去したもので、拡散前処理工程
などで一度消えたパターンを再生し、リングラフィ工程
が、前の拡散や酸化工程にひきつづいてできるようにし
たことである。
The present invention eliminates this drawback by regenerating the pattern that has disappeared in the pre-diffusion process and allowing the phosphorography process to be carried out following the previous diffusion and oxidation process.

以下、実施例をあげ、本発明について具体的に詳述する
EXAMPLES Hereinafter, the present invention will be specifically described in detail with reference to Examples.

第2図は本発明の実施例を図式化したものであり、拡散
前処理工程で一度消えたパターンを再生し、次のリング
ラフィ工程を可能にする工程の流れ図である。半導体材
料としてP型シリコンウェハー2を用いる。第1図点線
枠で示されるリングラフィ工程の後、ル型不純物8をイ
オン打込み装置などでドーピングする。次の不純物拡散
の前処理工程で酸化膜エツチングを過剰に行なうと、シ
リコン面上のパターンが見えにくくなったり見えなくな
ったりする。不純物8を熱拡散すると、シリコン面上の
パターンはほとんど見えない状態になる。
FIG. 2 is a diagrammatic representation of an embodiment of the present invention, and is a flowchart of a process for regenerating a pattern that has disappeared in the pre-diffusion process to enable the next phosphorography process. A P-type silicon wafer 2 is used as a semiconductor material. After the phosphorography step shown by the dotted line frame in FIG. 1, doping with a phosphor-type impurity 8 is performed using an ion implantation device or the like. If the oxide film is etched excessively in the pretreatment step for the next impurity diffusion, the pattern on the silicon surface becomes difficult to see or disappears. When the impurity 8 is thermally diffused, the pattern on the silicon surface becomes almost invisible.

そこで熱拡散により成長した酸化膜を、水で希たくした
7ツ酸で全面エツチングをして取り除き、次に水で希た
くした7ツ酸に対し硝酸を微量(濃度で1%以下程度)
混合したフッ硝酸液での化学的エツチング(以下スティ
ンエツチングと略す)を行なう。このエツチングにより
、P型、n型領域で着色が若干異なり、数秒後にパター
ンが現われる。次に水洗を行なったあと、アンモニア水
と過酸化水素を水で希たくした混合液を加熱して洗浄を
行なってから水洗し、乾燥して熱酸化をする。最初のス
ティンエツチングで、P型ンル型による着色の強弱によ
りパターンが現われるが、次のアンモニア水と過酸化水
素水の熱水洗浄処理では、このパターンがあまり見えな
い程度に、着色部のスティン膜がエツチングされる。し
かし最初のスティンエツチングのときついたシリコンウ
ェハー上のP型、n型領域の境界部の表面段差は、熱酸
化膜を形成してから次のリングラフィ工程でのレジスト
塗布したのちでも、鱈光機を通してシリコンウェハー面
上のマーカーを見ることができる程度に残っており、露
光可能となる。
Therefore, the oxide film that had grown by thermal diffusion was removed by etching the entire surface with hetamine diluted with water, and then a small amount of nitric acid (approximately 1% or less in concentration) was added to the diluted hetamine acid with water.
Chemical etching (hereinafter abbreviated as stain etching) is performed using a mixed fluoro-nitric acid solution. Due to this etching, the P-type and N-type regions are colored slightly differently, and a pattern appears after a few seconds. Next, after washing with water, washing is performed by heating a mixture of aqueous ammonia and hydrogen peroxide diluted with water, washing with water, drying, and thermal oxidation. In the first stain etching, a pattern appears depending on the strength and weakness of the coloring by the P type, but in the next hot water cleaning treatment with ammonia water and hydrogen peroxide, the stain film on the colored part is removed to the extent that this pattern is not very visible. is etched. However, the surface step at the boundary between the P-type and N-type regions on the silicon wafer, which was created during the first stain etching, cannot be removed even after the thermal oxide film is formed and the resist is applied in the next phosphorography process. The marker on the silicon wafer surface remains visible through the machine and can be exposed.

また、不純物拡散後には、うつすらとぶターンが見えて
いて熱酸化mll後後見えなくなった場合においても、
全面酸化膜を除去してから、スティンエッチを行ない、
アンモニア水と過酸化水素水の熱水洗浄処理をして、再
度熱酸化膜を形成すれば、次のリングラフィ工程が可能
となる。
In addition, even if a floating turn is visible after impurity diffusion and disappears after thermal oxidation,
After removing the entire oxide film, perform stain etch,
The next phosphorography process becomes possible by performing hot water cleaning treatment with ammonia water and hydrogen peroxide solution and forming a thermal oxide film again.

以上のごとく、本発明は、拡散前処理工程などで一度消
えた半導体面上のパターンな再生し、次のリングラフィ
工程を可能とするばかりでなく、パターン面上に着色に
よる色別を残さないというすぐれた効果をもつ。本実施
例は、化学的エツチング方法としてスティンエツチング
法を用いているが、他の化学的エツチングも同様に適用
できる。実施する半導体材料としては、化学的エツチン
グをおこす材料としては、化学的エツチングおこす材料
であればすべて可能であり、特にそのエツチングによっ
て半導体素子特性を著しく劣化させないような表面によ
る効果が少ないバイポーラトランジスター、ダイオード
、サイリスタ、バルクの電荷移動制御を行なう電界効果
トランジスタなどには十分適用できる。また、金属−酸
化物一半導体の三層構造をもつ電界効果トランジスタに
も適用できるが、半導体表面ダメイジによる電荷移動の
影響を考慮する必要がある。
As described above, the present invention not only reproduces the pattern on the semiconductor surface that has disappeared in the pre-diffusion process, etc., and enables the next phosphorography process, but also does not leave any color difference due to coloring on the pattern surface. It has an excellent effect. Although this embodiment uses stain etching as the chemical etching method, other chemical etching methods can be applied as well. Any semiconductor material that can be chemically etched can be used as long as it is a material that can be chemically etched, and in particular, bipolar transistors that have little effect due to the surface that does not significantly deteriorate the characteristics of semiconductor elements due to etching, It is fully applicable to diodes, thyristors, and field effect transistors that control bulk charge transfer. It can also be applied to a field effect transistor having a three-layer structure of metal-oxide-semiconductor, but it is necessary to consider the influence of charge transfer due to damage to the semiconductor surface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のリングラフィ工程を含む半導体装置の
製造工程の流れ図であり、第2図は本発明による拡散前
処理工程などで一度消えたパターンを再生し、次のリン
グラフィ工程を可能にする工程の流れ図である。 1は醸化膜、2はシリコンウェハー、3はレジスト、4
はガラス基板、5はマスクパターン、6は紫外線、7は
不純物拡散層、8は不純物、点線枠はリングラフィ工程
である。 以  上 出願人 株式会社睡訪精工舎 代理人 弁理士 最上  務 ス 第1図 第2図
Fig. 1 is a flowchart of a semiconductor device manufacturing process including a conventional phosphorography process, and Fig. 2 is a flow chart of a semiconductor device manufacturing process including a conventional phosphorography process, and Fig. 2 is a flowchart of the present invention, which reproduces a pattern that has disappeared in the diffusion pretreatment process and makes it possible to perform the next phosphorography process. It is a flow chart of the process of making. 1 is a fermented film, 2 is a silicon wafer, 3 is a resist, 4
5 is a glass substrate, 5 is a mask pattern, 6 is an ultraviolet ray, 7 is an impurity diffusion layer, 8 is an impurity, and the dotted line frame is a phosphorography process. Applicant Suiwa Seikosha Co., Ltd. Agent Patent Attorney Mogami Tsutomu Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] リングラフィ工程と次のリングラフィ工程の中間工程に
おいて、一度消失した半導体面上のパターンを再生処理
でパターンの再現をすることを特徴とする半導体装置の
製造方法。
1. A method for manufacturing a semiconductor device, characterized in that, in an intermediate step between a phosphorography step and a subsequent phosphorography step, a pattern on a semiconductor surface that has once disappeared is reproduced by a regeneration process.
JP57123331A 1982-07-15 1982-07-15 Manufacture of semiconductor device Pending JPS5913326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57123331A JPS5913326A (en) 1982-07-15 1982-07-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57123331A JPS5913326A (en) 1982-07-15 1982-07-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5913326A true JPS5913326A (en) 1984-01-24

Family

ID=14857910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57123331A Pending JPS5913326A (en) 1982-07-15 1982-07-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5913326A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5562996A (en) * 1990-06-27 1996-10-08 Gunze Limited Multi-layer films

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5562996A (en) * 1990-06-27 1996-10-08 Gunze Limited Multi-layer films
US5688456A (en) * 1990-06-27 1997-11-18 Gunze Limited Process for preparation of multilayer films

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