JPS59117169A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59117169A JPS59117169A JP22610482A JP22610482A JPS59117169A JP S59117169 A JPS59117169 A JP S59117169A JP 22610482 A JP22610482 A JP 22610482A JP 22610482 A JP22610482 A JP 22610482A JP S59117169 A JPS59117169 A JP S59117169A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- gate
- pattern
- region
- photo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、セルファライン構造のＧａＡｓＦＥＴの高耐
圧化のために好適な半導体装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device suitable for increasing the breakdown voltage of a GaAsFET having a self-line structure.
従来、０−ａＡ、５ＦＥＴの製造方法として、良く知ら
れているように、半絶縁基板上に、能動層を形成するた
めに、ｎ型となるイオン種を打込み、この能動層上にホ
トマスクによりソースドレインパターンを形成し、リフ
トオフ工程により、ソースドレイン電極を形成する。さ
らにソースドレイン電極の間に入るように、ゲート用の
ホトマスクを合せてパターンをきる。ゲート用金属を蒸
着しリフトオフ工程によりゲート電極を形成し、単体Ｆ
ＥＴを製作する。（ＥＤ２５，６．Ｐ２Ｓ５゜１９７８
）
ここで、ＦＥＴの耐圧を高く保ちつつ、高性能ＦＥＴを
つくるためには、Ｎ＋領領域ソース、ドレイン領域に形
成して、ソース抵抗を下げ、ドレインの電界集中を緩和
する。そのため、ゲートパターンに重ねて、ドレインに
耐圧用にスペースをとったりする手法がよく知られてい
る。Conventionally, as a well-known method for manufacturing 0-aA, 5FET, in order to form an active layer on a semi-insulating substrate, an n-type ion species is implanted, and a photomask is used to implant the ion species on the active layer. A source/drain pattern is formed, and a source/drain electrode is formed by a lift-off process. Furthermore, a pattern is cut using a photomask for the gate so that it will fit between the source and drain electrodes. A gate metal is vapor deposited and a gate electrode is formed by a lift-off process, and a single F
Produce ET. (ED25,6.P2S5゜1978
) Here, in order to create a high-performance FET while maintaining a high breakdown voltage of the FET, N+ regions are formed in the source and drain regions to lower the source resistance and alleviate the electric field concentration at the drain. For this reason, a well-known method is to overlap the gate pattern and provide a space for the drain to withstand voltage.
ゲートにホトレジパターンを重ねるときには、ソースド
レイン耐圧不良をさけるため、マスク合せ余裕を大きく
とる必要があり、デバイスサイズが大きくなるという欠
点がある。When overlapping a photoresist pattern on the gate, it is necessary to provide a large margin for mask alignment in order to avoid source-drain breakdown voltage defects, which has the disadvantage of increasing device size.
本発明の目的は、上記欠点を容易に解決する手段を提供
するもので、製造工程数を増加させずにマスク合せ余裕
を大きくとることなく Ｆ Ｅ Ｔのソース抵抗を下げ
ドレインゲート耐圧を維持する半導体装置の製造方法を
提供するものである。An object of the present invention is to provide a means to easily solve the above-mentioned drawbacks, and to lower the source resistance of FET and maintain the drain-gate breakdown voltage without increasing the number of manufacturing steps or taking a large margin for mask alignment. A method for manufacturing a semiconductor device is provided.
上記の目的を達成するため、本発明においては以下のよ
うに構成したことを特徴とする。In order to achieve the above object, the present invention is characterized by the following configuration.
Ｇ ａ Ａ ｓプロセスに於いて、ゲートパターンと高
濃ｉＮ型饋域形成用のホトレジストパターンを一部車ね
で、ドレイン側によせることにより、合せ余裕分一方の
マスク合だけにして、耐圧のためのサイズの瑠カロ分を
へらし、ソース抵抗を１氏くかつ、ソースゲート而１圧
不艮をおこ畑ないようにしている。In the GaAs process, by partially aligning the gate pattern and the photoresist pattern for forming the high-concentration iN type region to the drain side, the margin for alignment is limited to only one mask, and the withstand voltage is increased. The size of the gate is reduced, the source resistance is reduced by 1 degree, and the source gate does not require 1 pressure.
〔実施例〕
以下、本発明の一実施例を第１図により説明する。半絶
縁基板１の上にホトレジスト３を生布し、ホトマスクに
より穴開けし、ホトレジスト３をマスクＫ Ｓ＋等の不
純物をイオン打込みし、ｎ型領域２を形成する（ａ）。[Example] Hereinafter, an example of the present invention will be described with reference to FIG. A photoresist 3 is placed on a semi-insulating substrate 1, holes are made using a photomask, and impurities such as K S+ are ion-implanted into the photoresist 3 to form an n-type region 2 (a).
次に絶縁物列えばＰＥＧ膜４．５ｉＮｌｌ＠５、ＰＳＧ
暎６を形成し、ゲート用ホトマスクにより絶縁膜のエツ
チングの光によりＴ型パターンを形成する（ｂ）。ここ
でエツチングによつ−ｒＨＩ型パターンでもよい。この
後、菌濃度ト■型領域を選択的につくるため、ホトマス
クによりゲート反転の絶縁膜の上と耐圧に必要なドレイ
ンとの距離をとったホトレジストパターン９を形成し、
絶縁膜とホトレジストパターン９をマスクに、Ｓｉの不
純物をインプラ打込みによりソース領域７、トレイン領
域８に形成する（Ｃ１゜次にソース。Next, the insulator row is PEG film 4.5iNll@5, PSG
A T-shaped pattern is formed by etching the insulating film using a gate photomask (b). Here, an rHI type pattern may be used by etching. After this, in order to selectively create a germ-concentration T-shaped region, a photoresist pattern 9 is formed using a photomask with a distance between the gate inversion insulating film and the drain required for breakdown voltage.
Using the insulating film and photoresist pattern 9 as a mask, Si impurities are implanted into the source region 7 and train region 8 (C1°, then the source).
ドレイン配線用パターン形成用のホトレジストノくター
ン１０を形成し、ソースドレイン用の電極材料ＡｕＧｅ
／Ｎｉ／Ａｕ １１を蒸着、ホトレジストを利用したリ
フトオフをする（ｄｌ。A photoresist turn 10 for forming a pattern for drain wiring is formed, and an electrode material of AuGe for source and drain is formed.
/Ni/Au 11 is deposited and lift-off is performed using photoresist (dl.
次にホトレジストを除去後、ホトレジストを全面塗布し
、ゲート反転用のパターンのＰＳＧ膜４の上部ができる
ようにプラズマエッチする（ｅｌ。Next, after removing the photoresist, photoresist is applied to the entire surface and plasma etched to form the upper part of the PSG film 4 in a pattern for gate inversion (el.
次にゲート反転用のパターンのＰＥＧ膜６．８ｉＮ膜５
、ＰＥＧ膜４を順番にエツチングする。Next, the PEG film 6.8iN film 5 of the pattern for gate inversion
, PEG film 4 is etched in order.
このあと全面にゲート電極拐料Ａｔ等を蒸着し、リフト
オフにより、ゲート１２を形成する（ｆｌ。After that, a gate electrode removal material At or the like is deposited on the entire surface, and the gate 12 is formed by lift-off (fl.
以上の説明ではゲート反転型プロセスでめるがゲート金
属例えばＴｉＷを先につけるプロセスにおいても同様で
ある。Although the above description is based on a gate inversion type process, the same applies to a process in which a gate metal such as TiW is added first.
又、以上の説明では半絶縁基板に能動層を形成している
が、エピタキシャル基板において、能動層をメサエッチ
して使用すれば、上ｎ１シプロセスに使用できる。Further, in the above description, the active layer is formed on a semi-insulating substrate, but if the active layer is mesa-etched and used on an epitaxial substrate, it can be used in the upper n1 process.
以上のように、Ｔ型とか■型ゲートパターンにより、高
濃度Ｎｍ餉域を形成したためにおきるゲートソース耐圧
不良を々〈シ、ソース抵抗を実用上の最小とし、ドレイ
ン側にホトレジストをつけることによりドレインゲート
間の距離を離し、ドレイン面す圧を商めることかできる
。As described above, gate-source withstand voltage failure caused by forming a high concentration Nm region with a T-type or ■-type gate pattern can be reduced by reducing the source resistance to a practical minimum and applying photoresist on the drain side. It is possible to increase the distance between the drain gate and reduce the pressure on the drain surface.
本発明によれば、ホトレジスト工程で、ゲートパターン
の一部とドレイン側を覆うため、ソース側はゲートパタ
ーンの１則まで高濃度のＮ型拳域を形成でき、ソース抵
抗を下げられる。一方ドレイン１則はゲルドパクー７も
マスクとなるため、ゲートパターンのドレイン端と尚濃
度のＮ型領域を形成しないための保膿用ホトレジストパ
ターンの合せがマスク合せ余裕以上あれば、耐圧に必要
なスペースと片側のみの合せ余裕ですむという効果があ
る。According to the present invention, since a part of the gate pattern and the drain side are covered in the photoresist process, a high concentration N-type region can be formed on the source side up to the first rule of the gate pattern, and the source resistance can be lowered. On the other hand, according to the drain rule 1, GELDOPAKU 7 also serves as a mask, so if the alignment of the drain end of the gate pattern and the photoresist pattern for purulent retention to prevent the formation of a high-concentration N-type region is greater than the mask alignment margin, the space required for withstand voltage is This has the effect of requiring only one side of the alignment margin.
第１図は本発明に係るＱ ａ Ａ ｓ Ｆ Ｅ Ｔ
の製造工程とその断面である。
１・・・半絶縁基板、２・・・ｎ型領域、３・・・ホト
レジスト、４・・・ＰＥＧ膜、５・・・ＳｉＮ膜、６・
・・ＰＳ（）膜、７・・・ソース領域、８・・・ドレイ
ン領域、９・・・ホトレジストパターン、１０・・・ホ
トレジストパターン、１１−＃、ｕＯｅ／Ｎｉ／Ａｕ、
１２・・・ゲート。 ノ・、代理人 弁理士 瀕
Ｈ」利幸・；FIG. 1 shows Q a A s F E T according to the present invention.
This is the manufacturing process and its cross section. DESCRIPTION OF SYMBOLS 1... Semi-insulating substrate, 2... N-type region, 3... Photoresist, 4... PEG film, 5... SiN film, 6...
... PS () film, 7... Source region, 8... Drain region, 9... Photoresist pattern, 10... Photoresist pattern, 11-#, uOe/Ni/Au,
12...Gate.ノ・、Representative Patent Attorney Toshiyuki;
Claims (1)
上の多層膜からなるゲートパターンを形成する工程と、
ゲートパターンの一部とドレイン領域となる動作領域の
一部をホトレジストで覆う工程と、前記ホトレジストと
ゲートを形成する多層膜のゲートパターンをマスクとし
て、冒′ａ度の不純物領域を形成することを特徴とする
半導体装置の製造方法。1. Forming a gate pattern consisting of two or more multilayer films on a semi-insulating substrate having an operating region;
A step of covering a part of the gate pattern and a part of the active region that will become the drain region with photoresist, and using the photoresist and the gate pattern of the multilayer film forming the gate as a mask, forming an undesired impurity region. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22610482A JPS59117169A (en) | 1982-12-24 | 1982-12-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22610482A JPS59117169A (en) | 1982-12-24 | 1982-12-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59117169A true JPS59117169A (en) | 1984-07-06 |
Family
ID=16839885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22610482A Pending JPS59117169A (en) | 1982-12-24 | 1982-12-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117169A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63313870A (en) * | 1987-01-20 | 1988-12-21 | インターナショナル・スタンダード・エレクトリック・コーポレイション | Self-aligning field effect transistor and manufacture of the same |
-
1982
- 1982-12-24 JP JP22610482A patent/JPS59117169A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63313870A (en) * | 1987-01-20 | 1988-12-21 | インターナショナル・スタンダード・エレクトリック・コーポレイション | Self-aligning field effect transistor and manufacture of the same |
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