JPS59101096A - Storage circuit - Google Patents

Abstract

PURPOSE:To attain the cost down of a storage circuit using a nonvolatile memory and the miniaturization of packaging by forming two kinds (high and low) voltages from a power supply voltage and applying any of the voltages to a control gate depending on the logical state of data input terminals. CONSTITUTION:When ''H'' is applied to a terminal IN, an output of an AND gate 1 goes to a VDD as shown in Fig. A to turn on a TR9. Further, an ''H'' output of the gate 1 is inverted to turn off a TR4, resistors 5, 6 do not function as a voltage dividing circuit, an output level of a voltage switching circuit 2 goes to a power supply VDD, a write current is applied to a memory cell 8 and its threshold voltage is increased from a VTHS to a VTHA. In the readout of a memory cell after the end of write, since no ''H'' is applied to an enable terminal EN other than at write, the TR4 is turned on, and the output level of the circuit 2 becomes VDD, decreased from the power supply VDD. Since the setting is made in advance as VTHS<VDD'<VTHA, the cell 8 under no write state is turned on, its output goes to 0V and the output of the cell 8 finished for write goes to the VDD as shown in Fig. C.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses non-volatile memory and eliminates the need for a high-voltage power supply bottle during packaging, thereby creating a large memory circuit that can be miniaturized.

The present applicant previously proposed various electronic control circuits for the middle cylinder, such as a run 775181 circuit that flashes a lamp for a fixed period of time 111J when the drive switch is turned on; : Is it possible to use a dedicated circuit for the limited speed Δ-bar alarm circuit that compares the JRuru room lamp timer circuit or the set frequency and the set frequency and drives the dimming when the two frequencies match? 1・
We proposed a programmable integrated circuit that can be assembled using L output circuits.

This programmable integrated circuit has an oscillation circuit that generates a clock signal as a time reference, a programmable counter that is controlled in increments by the output of the oscillation circuit, an input terminal, an output terminal, Was the oscillation circuit inserted into the connection path between the counter? ! It is integrated and formed by /υ including two numbers 1 to 1 and a memory circuit that stores the set value data of the programmable counter and the control signal to each of the programmable counters, and the memory contents of the memory circuit are The system is designed to operate accordingly and determine which one to use.

By the way, as a memory circuit, the memory cell is Pr<o
When M<for example, fuse type), EPROM (for example, FAMO8 with a control gate), FEPROM (for example, 'MNO3), etc. When injecting carriers into the trap near the boundary W surface A, a voltage higher than the voltage required for normal circuit operation is generally required. In addition to the external terminal for circuit operation, it was necessary to provide an external terminal for a high-voltage power supply and apply the high-voltage power to the memory cell during writing.

However, in such conventional memory circuits,
Since it is necessary to supply two power sources, high and low, from the outside, if you want to minimize the number of IC bins, for example, a 4-bin DIRIC package, one output bin and one output bin.
, 1 earth bottle.

In order to introduce rewritable non-volatile memory into such an IC package, it is necessary to add one high-voltage power supply bin, so if you want to make the circuit operation power supply bin stand out, it is necessary to add one high voltage power supply bin. There are problems in that the increase in area lowers the yield, leading to losses of 1 to 100%, and further increases the size of the package.

The present invention was made in view of these conventional problems, and its purpose is to reduce the cost of memory circuits using this type of non-volatile memory and to reduce the packaging size. The aim is to achieve this goal.

In order to achieve the above object [1], the present invention steps down the power supply voltage applied to the external power supply input terminal to form two voltages, high and low, and outputs either of them depending on the logic state of the data input terminal. The device is characterized in that it has a built-in voltage switching circuit for switching, and the output voltage of this voltage switching circuit is applied to the control gate of the nonvolatile memory.

A preferred embodiment of the present invention will be explained in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an example of a memory circuit according to the present invention. In the same figure, AND gate 1 is an address signal (for specifying a memory cell) supplied to an enable terminal "N".
, and is configured to pass logic data supplied to the data input terminal IN. Further, this AND gate 1 is operated by an external power supply supplied to the power supply terminal Voo.

Next, the voltage switching circuit 2 includes an inverter 3 that inverts the output of the AND gates 1 to 1, a MOS I-transistor 4 whose opening and opening are controlled by the output of the inverter 3, and a MOS
Two voltage dividing resistors 5 and 6 are connected in series between the L-transistor 4 and the power source Voo, and the potential at the connection point between these two resistors 5 and 6 is output.

Therefore, when the output of AND goo 1-1 is 1'', transistors 1 to 4 are turned off and the voltage switching circuit 2 directly outputs the power source Voo, whereas the output of AND goo 1-1 is When the output is in the L'' state, the transistor 4 is turned on and the power supply VDD is voltage-divided and stepped down to Voo- by the resistors 5 and 6, and then output.

Next, the memory section 7 is inserted between a non-volatile 1'' memory cell 8 to which the output voltage of the voltage switching circuit 2 is applied to the controller 1 and the external output terminal VDD and the memory cell 8. , and the MOS l-transistor 9 for supplying cell power, which is free depending on the logic state of the outputs of the A N +) groups 1 to 1, and the external power input terminal V.
A MO serving as a load resistor is inserted between the memory cell 8 and the MO8I in parallel with the transistor 9.
It is composed of transistors 10 and 10, and a signal corresponding to the voltage drop across the multiple MOS transistors 1o is outputted from an external output terminal OU-1 as a load resistor.

Next, FIG. 2 shows a cross section of a specific semiconductor structure of the memory cell 8, in which 11 is a substrate, 12 is a drain region, 13 is a source region, 14 is a goo-1-oxide film, 15 is a floating gate.

16 is the second oxide film, 17 is the control group 1-218
1 is an interlayer insulating film, 19 is a drain IJj, and 20 is a source electrode.

As is clear from the same figure, this non-volatile matrix 8 is connected to the floating group 1 to Il.
? The write voltage is -(
is used as a VCG for control goo 1-17 (20-2
5V), and Voo to the drain electrode 19 (2 to 20V).
)is necessary. In addition, it is several tens of liters as an old 04 room.
s is required.

The threshold voltage of this memory i-transistor is 1"-2V (VTHB) before writing and writing, and more than ten V (VTHB) after writing.
I-1^).

Therefore, the voltage VCG to control group 1 during reading must satisfy VTHB<VCG<VTHA (1).

Assuming that the power supply voltage during writing is 25V and the power supply voltage during reading is 12V, in order for the circuit in the circuit to operate even at the power supply voltage of 21V, it must have a withstand voltage of 30V or more. lv
It is necessary to form the 111th transistor with l OS transistor.

Next, the operation of the memory circuit composed of the above lf4 configuration will be explained with reference to the waveform diagram of FIG.

First, connect the enable terminal EN of AND 1 to 1.''
is supplied (at the time of writing), a pulse width sufficient for writing (for example, number + nts) is supplied to the arter input terminal IN.
When the ``1-bi'' pulse is supplied, the third
As shown in FIG.
o), and this output turns on the transistor 9.

Furthermore, when the output of the AND gate 1 is turned off, this "Hr+ output horn is inverted to 11+1 by the inverter 3, and then supplied to the IF2 to the gates of the resistors 1 to 4 to turn them off. Then, the resistor 5, The voltage dividing circuit formed by the groove 6 no longer functions as a voltage dividing circuit, the voltage switching circuit 2 outputs the power source Voo as it is, and this output is supplied to the control gate of the memory cell 8. A virtual write current is supplied to the memory cell 8, and the threshold voltage of the memory cell 8 becomes VTH.
B to VTHA.

Next, after the above writing is completed, when reading the memory contents of the memory cell, the output of the △ND gate 1 is low since 1°' is not supplied to the enable terminal EN except during writing. By becoming It, the transistor 4 is turned on, and the voltage dividing circuit formed by the resistor 5.6 functions, so that the voltage is cut off (It, from the circuit 2, the power supply V o o
The voltage is stepped down to h' V o o- and output.

Here, the value of the second power supply voltage vDD' is set in advance so that VTHB<VDD-<VTHA.

Therefore, in the memory cell 8 to which writing has not yet been performed, the value of the voltage Voo'' is the threshold level V T of the memory cell 8, as shown in FIG. 3(B). Hs J: The memory cell 8 is turned on due to the large current, and the output OUT is "L" (OV), whereas the 3rd level of the Ic memory and recell 8 which has already been written is As shown in figure (C), the control gate voltage V
The value of oo- becomes larger than the threshold voltage VTHA, and the memory cell 8 enters the A off state, and its output voltage jO
UT becomes "'l-1" (Voo).

In this way, in this embodiment, the external power supply terminal Voo
Supplied from 1. : By lowering the power supply voltage internally, the first. Second power supply voltage V.

o, Voo" and are switched and supplied to control groups 1-8 as appropriate in response to the write pulse, so unlike conventional memory circuits, two types of power supply voltages can be externally connected. Since it is not necessary to provide two power supply terminals for the
It becomes possible to store it in the IR package, and
In addition, by reducing the surface area of the pads formed on the IC substrate, yields can be improved and costs can be reduced.
It is something that

In addition, the actual hI! In example i, the voltage switching circuit 2 was configured by further connecting Mo5t to two resistors connected in series and activating it or inactivating it. As shown in the figure, the power supply V
Two resistors 5a and 5a are connected in series between oρ and ground, and can be turned on and off alternately via an inverter (21). Power supply voltage V through the transistor
A similar function can be achieved by configuring the voltage divider circuit to selectively output the potential at the connection point of the voltage dividing circuit.

As is clear from the above description of the embodiments, according to the present invention, it is possible to implement a 4-bin package of an IC storage circuit using nonvolatile memory cells. This improves the yield and makes it possible to reduce rice 1 to 1 down.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a memory circuit according to the present invention, and FIG. 2 is a semiconductor cross section 1f of a non-JiF-emitting memory cell.
FIG. 3 is a signal waveform diagram of each part for explaining the operation of the memory circuit of the present invention, and FIG. 4 is a circuit diagram showing another example of the voltage switching circuit. 2... Voltage switching circuit 8... Memory cell 9... MOS l- for cell power supply
Transistor 10...M that functions as a zero load resistance
OS transistor IN... Data input terminal OUT... Output terminal) Child patent applicant I" San Jidosha Co., Ltd.

Claims (1)

[Claims] (1) An external power supply input terminal to which a power supply voltage is applied; a data input terminal to which logical data to be written is input; the power supply voltage applied to the external power supply input terminal is stepped down to provide two types of high and low voltages; a voltage switching circuit that forms a voltage and outputs one of the voltages depending on the logic state of the data input terminal; memory cell: a cell power supply gate that is inserted between the external power input terminal and the memory cell and turns on and off depending on the logic state of the data input terminal; the external power input terminal and the memory cell; A load resistance element inserted in parallel to the hill power supply gate 1 between the cells; and an external output 9 from which a signal corresponding to the voltage drop of the load resistance element is derived. q that! Memory circuit with J sign.