JPS5891572A - 仮想計算機のアドレス変換方式 - Google Patents

仮想計算機のアドレス変換方式

Info

Publication number
JPS5891572A
JPS5891572A JP56190329A JP19032981A JPS5891572A JP S5891572 A JPS5891572 A JP S5891572A JP 56190329 A JP56190329 A JP 56190329A JP 19032981 A JP19032981 A JP 19032981A JP S5891572 A JPS5891572 A JP S5891572A
Authority
JP
Japan
Prior art keywords
address
computer
virtual
address translation
identifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56190329A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0235338B2 (enrdf_load_stackoverflow
Inventor
Shinji Nanba
難波　信治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56190329A priority Critical patent/JPS5891572A/ja
Publication of JPS5891572A publication Critical patent/JPS5891572A/ja
Publication of JPH0235338B2 publication Critical patent/JPH0235338B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56190329A 1981-11-27 1981-11-27 仮想計算機のアドレス変換方式 Granted JPS5891572A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56190329A JPS5891572A (ja) 1981-11-27 1981-11-27 仮想計算機のアドレス変換方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56190329A JPS5891572A (ja) 1981-11-27 1981-11-27 仮想計算機のアドレス変換方式

Publications (2)

Publication Number Publication Date
JPS5891572A true JPS5891572A (ja) 1983-05-31
JPH0235338B2 JPH0235338B2 (enrdf_load_stackoverflow) 1990-08-09

Family

ID=16256370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56190329A Granted JPS5891572A (ja) 1981-11-27 1981-11-27 仮想計算機のアドレス変換方式

Country Status (1)

Country Link
JP (1) JPS5891572A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0235338B2 (enrdf_load_stackoverflow) 1990-08-09

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