JPS5889850A - Face mounting type semiconductor device - Google Patents
Face mounting type semiconductor deviceInfo
- Publication number
- JPS5889850A JPS5889850A JP56187030A JP18703081A JPS5889850A JP S5889850 A JPS5889850 A JP S5889850A JP 56187030 A JP56187030 A JP 56187030A JP 18703081 A JP18703081 A JP 18703081A JP S5889850 A JPS5889850 A JP S5889850A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- leads
- substrate
- package
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は面実装置半導体装置に関する。[Detailed description of the invention] The present invention relates to a surface-mounted semiconductor device.
半導体装置の一形態として、第1図に示すように、パッ
ケージ10両側面から一歇のり一ド2を突出させ、かつ
各リード2は途中、でパッケージ1の下面側の方向に折
れ曲がった、いわゆるデエアルインライン形の半導体装
置が知られている。この構造の半導体装置3は、配線基
板等の基板に実装する場合には、下方に延在するリード
2の先端部を基鈑の挿入孔に挿し込むとともに、半田に
よって固定し【いる。As one form of a semiconductor device, as shown in FIG. 1, one lead 2 is protruded from both sides of a package 10, and each lead 2 is bent halfway toward the bottom of the package 1. A distributed in-line type semiconductor device is known. When the semiconductor device 3 having this structure is mounted on a substrate such as a wiring board, the tips of the leads 2 extending downward are inserted into the insertion holes of the base plate and fixed with solder.
ところで、近年、実装スペースの縮小化に伴ない、第2
図で示すように、リード2の先端面を基板4上に対面截
置した状態で半田5を用いて固定するいわゆる面実装構
造が採用されている。By the way, in recent years, as the mounting space has become smaller, the second
As shown in the figure, a so-called surface mount structure is adopted in which the leading end surfaces of the leads 2 are placed facing each other on the substrate 4 and fixed using solder 5.
しかし、従来の半導体装置3は、リード2の先端を基板
の挿入孔に挿し込むことを前提としているため、第3図
に示すようにリード2の先端は面取りが施こされ、先端
は尖っている。このため、実装時の半田唖の接着材料と
のwI曽面積が少なく、接合強度が低い。また、パッケ
ージがレジンで形作られ、基板がセラミックあるいは紙
フェノールである場合には、パッケージと基板との熱膨
張係、数の差による熱応力がリード接合部に加わり、リ
ードが基板から剥離してしまい、いわゆる断線モードと
呼ぶ不良が発生し易くなる。However, since the conventional semiconductor device 3 is based on the assumption that the tips of the leads 2 are inserted into the insertion holes of the substrate, the tips of the leads 2 are chamfered and sharpened, as shown in FIG. There is. Therefore, the wI area of the solder gap with the adhesive material during mounting is small, and the bonding strength is low. Additionally, if the package is made of resin and the substrate is ceramic or paper phenol, thermal stress due to the difference in thermal expansion coefficient and number between the package and the substrate will be applied to the lead joint, causing the leads to separate from the substrate. As a result, a defect called a so-called disconnection mode is likely to occur.
したがって、本実廟の目的は実験時断線モード不良が生
じにくい構造の牛導体装置を提供することにある。Therefore, the purpose of this study is to provide a conductor device with a structure that is unlikely to cause disconnection mode failures during experiments.
このような目的を達成するために本発明は、パッケージ
と、このパッケージの側面から突出するとともに、パッ
ケージの上面あるいは下面方向に折れ曲がって延在する
複数のリードと、からなり、かつ基板への実装にあって
は、リード先端面を基板面に対面させて接着材料で固定
する面実装″漏半導体装置において、前記各リードの′
半田溶着領域には貫通孔あるいは凹凸部を設けてなるも
のであって、以下実施例により±発明を説明、する。In order to achieve such an object, the present invention comprises a package and a plurality of leads that protrude from the side surface of the package and extend bent toward the top or bottom surface of the package, and that are mounted on a substrate. In a surface mount "leakage semiconductor device" in which the lead end face faces the substrate surface and is fixed with an adhesive material, the
The solder welding area is provided with through holes or uneven portions, and the invention will be explained below with reference to Examples.
第4図は本発明の一実施例による半導体装置の斜視図で
あり、第5図は同じく実装状態でのリード先端部を示す
一部の説明図である。FIG. 4 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a partial explanatory view showing the lead tips in a mounted state.
第4図に示す牛導体装置は、デュアルインライン形とな
っている。すなわち、レジンからなるパッケージ1の両
側面から突出する複数のり−ド2は途中から全て下方(
ある−いは上方)に向かって突出している。また、各リ
ード2の先端部、すなわち実装時に半田が濡れる半田溶
着領域には貫通孔6が設けられている。The cow conductor device shown in FIG. 4 is of a dual in-line type. That is, the plurality of glues 2 protruding from both sides of the package 1 made of resin are all downward (
protrudes upward). Further, a through hole 6 is provided at the tip of each lead 2, that is, in a solder welding region where solder gets wet during mounting.
このような構造の半導体装置を基板(配線基板)に実装
した状態にあっては、第5図に示すように、各リード2
の先端部は先端面を基板(配線基板)4に対Wi載装さ
れた状態で半田5によって基板4に固着される。この際
、半田5はリード2の半田溶着領域に設けられた貫通孔
6部分内にも入り込む。この結果、リード2と半田3と
の接触面積が増大して接合強度が向上するばかりでなく
、半田3で貫通孔6部分を介してリード先端部を被うた
め、リード2の剥離時には従来のリード2と半田5との
界面の剥れ(剪断力)以外に半田の引張破壊をも生じさ
せなければならなくなり、接合強度は従来に比較して大
幅に増大する。したがって、温度サイクル試験における
熱応力によっても、リード2が基板4から剥離すること
はなくかり、断線モード不良の低減化が図れる。When a semiconductor device having such a structure is mounted on a board (wiring board), each lead 2 is connected as shown in FIG.
The tip end is fixed to the substrate 4 with solder 5 with the tip surface mounted on the substrate (wiring board) 4. At this time, the solder 5 also enters into the portion of the through hole 6 provided in the solder welding area of the lead 2. As a result, not only does the contact area between the lead 2 and the solder 3 increase and the bonding strength improves, but also the solder 3 covers the lead tip through the through hole 6, so when the lead 2 is peeled off, it is difficult to In addition to peeling (shearing force) at the interface between the lead 2 and the solder 5, it is also necessary to cause tensile failure of the solder, and the bonding strength is significantly increased compared to the conventional method. Therefore, the leads 2 do not peel off from the substrate 4 even due to thermal stress in the temperature cycle test, and disconnection mode failures can be reduced.
なお、本発明は前記実施例に限定されない。たとえば、
第6図IJII 、t (blに示すように、リード2
の半田溶着領域(ハツチングを施した領域)7に側面あ
るいは下面から溝8を入れ、凹凸部を設けて半田との接
合強度を向上させるようにしてもよい。Note that the present invention is not limited to the above embodiments. for example,
Figure 6 IJII, t (as shown in bl, lead 2
A groove 8 may be formed in the solder welding area (hatched area) 7 from the side or bottom surface to provide an uneven portion to improve the bonding strength with the solder.
また、本発明はデュアルインライン形について説明した
が、パッケージの全周面からリードが突出する構造等の
半導体装置にも適用できるiさらに、接着材料は半田以
外のものでもよい。Further, although the present invention has been described with respect to a dual in-line type, it can also be applied to a semiconductor device having a structure in which leads protrude from the entire circumferential surface of the package.Furthermore, the adhesive material may be other than solder.
以上のように、本発明によれば、面実装時に断線モード
不良が生じにくい構造の半導体装置を提供することがで
きる。As described above, according to the present invention, it is possible to provide a semiconductor device having a structure in which disconnection mode failures are less likely to occur during surface mounting.
第1図は従来の半導体装置の斜視図、第2図は同じく面
実装状態を示す側面図、第3図は同じくリード先端部の
斜視図、第4図は本発明の一実施例による面実装飄の半
導体装置を示す斜視図、第5図は同じく基板に面実装し
た状態におけるリード先端゛部を示す説明図、第6図i
ll 、 (blは他の実施例におけるリード先端部を
示す斜視図である。
1山パツケージ、2・・・リード、3・・・半導体装置
、4・・・基板、5・・・半田、6・・・貫通孔。FIG. 1 is a perspective view of a conventional semiconductor device, FIG. 2 is a side view showing a surface-mounted state, FIG. 3 is a perspective view of a lead tip, and FIG. 4 is a surface-mounted device according to an embodiment of the present invention. FIG. 5 is an explanatory diagram showing the lead tips in a state where the semiconductor device is surface-mounted on a substrate, and FIG. 6
ll, (bl is a perspective view showing a lead tip in another embodiment. Single package, 2... Lead, 3... Semiconductor device, 4... Substrate, 5... Solder, 6) ...Through hole.
Claims (1)
とともに、パッケージの上面あるいは下面方向に折れ曲
がって延在する複数のリードと、からなり、かつ基板へ
の実装にあっては、リード先端面を基板面に対面させて
接着材料で固定する面実装−半導体装置において、前記
各リードの半田溶着領域には貫通孔あるいは凹凸−を設
けてなることを特徴とする面実装製半導体装置。 2、パッケージはレジンからなることを特徴とする特詐
−求の範囲第1項記戦の面実装蓋牛導体装置。[Claims] 1. Consisting of a package and a plurality of leads that protrude from the side surface of the package and bend and extend toward the top or bottom surface of the package, and when mounted on a board, A surface-mounted semiconductor device in which a lead end face faces a substrate surface and is fixed with an adhesive material, characterized in that a through-hole or an unevenness is provided in a solder welding area of each lead. . 2. A surface-mounted cover conductor device according to item 1 of the scope of special fraud, characterized in that the package is made of resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187030A JPS5889850A (en) | 1981-11-24 | 1981-11-24 | Face mounting type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56187030A JPS5889850A (en) | 1981-11-24 | 1981-11-24 | Face mounting type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5889850A true JPS5889850A (en) | 1983-05-28 |
Family
ID=16198956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56187030A Pending JPS5889850A (en) | 1981-11-24 | 1981-11-24 | Face mounting type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5889850A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144243U (en) * | 1984-02-29 | 1985-09-25 | 日本電気ホームエレクトロニクス株式会社 | Mounting structure of DIP type IC |
| JPS60187557U (en) * | 1984-05-24 | 1985-12-12 | 株式会社 フジソク | Micro electronic components |
| JPS61114848U (en) * | 1984-12-28 | 1986-07-19 | ||
| JPH0736434B2 (en) * | 1985-10-31 | 1995-04-19 | モトローラ・インコーポレーテッド | Surface mountable integrated circuit package with solder retention leads |
| JP2017092496A (en) * | 2017-01-31 | 2017-05-25 | 株式会社村田製作所 | Component module |
| JP2021034324A (en) * | 2019-08-29 | 2021-03-01 | 矢崎総業株式会社 | Shield connector |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698856A (en) * | 1980-01-11 | 1981-08-08 | Hitachi Ltd | Semiconductor resistance device |
-
1981
- 1981-11-24 JP JP56187030A patent/JPS5889850A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5698856A (en) * | 1980-01-11 | 1981-08-08 | Hitachi Ltd | Semiconductor resistance device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60144243U (en) * | 1984-02-29 | 1985-09-25 | 日本電気ホームエレクトロニクス株式会社 | Mounting structure of DIP type IC |
| JPS60187557U (en) * | 1984-05-24 | 1985-12-12 | 株式会社 フジソク | Micro electronic components |
| JPS61114848U (en) * | 1984-12-28 | 1986-07-19 | ||
| JPH0736434B2 (en) * | 1985-10-31 | 1995-04-19 | モトローラ・インコーポレーテッド | Surface mountable integrated circuit package with solder retention leads |
| JP2017092496A (en) * | 2017-01-31 | 2017-05-25 | 株式会社村田製作所 | Component module |
| JP2021034324A (en) * | 2019-08-29 | 2021-03-01 | 矢崎総業株式会社 | Shield connector |
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