JPS5887866A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement in withstand voltage of a substrate PNP transistor by a method wherein, in regard to the substrate PNP transistor to be formed inside an IC, a part of an I<2>L process is utilized. CONSTITUTION:An n type layer (region) 6 is formed by introducing n type impurities into an n<-> type layer 2a for the purpose of preventing the diffusion of boron contained in a substrate 1 into the n<-> type layer 2a. As a result, ''boiling- up diffusion'' of the B (boron) coming from a p type substrate is compensated by selectively introducing the n type impurities into the lower part of an epitaxial n<-> layer, the hFE of the PNP transistor on the substrate is reduced, the withstand voltage thereof is improved, and the yield rate in the wafer stage is also improved. The introduction of said n type impurities can be performed without changing the process of manufacture by using an I<2>L processing in common.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device (IC), and particularly to an IC.
Regarding the sub-stray (PNP) transistor formed within the transistor.

I including transistor and MOS F E 'l'
In C, a PNP transistor structure in which a part of the P-type substrate (substrate) σ) is used as the collector was proposed by the applicant and others.

This is shown in Figure 1 (on small side 5, P1%lJ 1-
forming an N-type layer 2 grown on
P-type diffusion layer 3 connected from the surface of the N-type layer 2 to the P-type substrate
C1 is surrounded by this isolation part as an isolation part.
^What-Mituta, N4 type area 5 with base extraction 1■ and (7
, P
：Uwoko l/Kita take-out part and Shidamo θ).

By the way, Baiboratfunjista O, Nibi MOS F
In the case of I C containing I=: l', the N-type layer formed by epitaxial growth is relatively thin (for example, 7 to 1
0 μm), its ``two-standard knee γI Cσ) r-mi, gate oxidation, etc. after diffusion θ) heat rod horn',! Ill
-J) filtration, 8 (+I
1) As a result of the diffusion, the above-mentioned substrate 1
3 N P 1. →The base width WB of the transistor becomes smaller 1. In the case of a standard: near ICυ')NPN) transistor, an N4 type buried layer is formed between the P type substrate l and the N- type layer 2.2. Therefore, it is possible to provide a certain degree of withstand voltage (approximately 8 V), but in the case of substrate I) N P ) transistors, there is no N++ buried layer, so if the base width WB is extreme, fr There was a problem.

The present invention has been made in consideration of the above problems,
The purpose is to improve the withstand voltage of the substrate PNP transistor by using a part of the I''L process.

Figure 2 shows the subs) l/-) P N according to the present invention.
This figure shows the basic structure of a P transistor. 1st
The conventional substray shown in the figure 1- p NP
) The difference from a transistor is that in order to prevent boron in the substrate 1 from being diffused into the base N-type layer 2a, an N-type impurity is introduced into the N-type layer 2a to form an N-type layer (region). 6 was formed.

FIG. 3 shows the impurity concentration distribution in the AA cross section of FIG. 2.

FIG. 4 shows an embodiment of a bipolar MO8IC in which a 12L vertical NPN transistor and a substrate PNP transistor are incorporated on a common substrate. (M.O.S.
(FE'1' is omitted in the drawing) These are partially formed on the 7F of the P-type substrate 11 via the NF-type buried layers 12a, 12b.

13c) is epitaxially grown, and the respective elements are incorporated in each semiconductor region separated by P-type isolation portions t4a, 14b-.

Among these, in I'L, N-type 1@1: (A P-type diffusion layer 15 is formed on the surface of a to serve as an injector, and other P-type
Based on the diffused diffusion layer 16, N″ type diffused layer 17 collector,
As an N″ type several-dispersion layer emitter extraction part (not shown), N
Configure a PN inverter. In this I''L, in order to improve the current amplification factor βl of the inverse transistor, a KN+ type buried layer 1 is used before forming the N- type (epitaxial) layer.
Form N layer 18 on 2a by phosphorus ion implantation-C
Ru.

N'' type layer 13 in the transistor
A P-type diffusion layer 19 is formed on the surface of a to serve as a base, and N'
- type diffusion layers 20 and 21 are used as emitter and collector extraction parts.

In substratum) PNP) transistor, N one layer 1
A P-type diffusion layer 22.3a is formed on the surface of the P-type diffusion layer 22. The N+ type scattering layer 23 is formed to serve as an emitter and base extraction portion, and the P type-γ isowarf 3f portion 14c is used as a collector extraction portion. This PNP
The N-type region 24 for maintaining the breakdown voltage of the transistor can be formed using the ion implantation process of the 12L N-type region 18.

According to the present invention described in the embodiments above, by selectively introducing N-type impurities into the lower part of the epitaxial N layer, P
It compensates for the upward diffusion of B (boron) from the mold substrate, lowers the hFF of the substrate (PNP) transistor, improves the withstand voltage, and improves the yield at the wafer stage. This N-type impurity introduction can be carried out without changing the process by sharing the I''L process.

Incidentally, as shown by the dotted line A in FIG. 4, after the formation of the N-type layer 13, an N-type impurity may be introduced into the N-type layer 13a by ion implantation. This N-type impurity (5)
The introduction of RI/'1/% can be carried out simultaneously with the introduction of the N-type impurity for improving βi, as shown by the dotted line A2 in FIG.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view showing an example of a P N P transistor (Sabstra), and Fig. 2 is a cross-sectional view of a P N P transistor (Sabstra) according to the present invention.
A cross-sectional view showing the HJIH structure of a PNP transistor. Figure 3 is an impurity concentration distribution curve diagram corresponding to the A-A cross section in Figure 2. Figure 4 is a bipolar (MOS) I'LIC.
FIG. 2 is a sectional view of an embodiment in which the present invention is applied. l-Pm&&, 2...N type epitaxial 14m, 3
...P-type isolation section, 4...P-type emitter, 5
・・N++ base extraction part, 6 N type impurity ion implantation region, 11 ・P type substrate, 12a, 12b ・・N4 type buried layer, 13a, +31), ,, N− type epitaxial layer, 14 a, 14 b, -P type aisle section, 15.P type injector, 16..P type base, 17.N'''' collector, 18..N type area, 19.P
Type base, 20.N'' emitter, 21-N'' type collector extension section, 22.P jJ'' emitter, 23 (6)...N+ type base extraction section, 24.N type region. Agent Patent Attorney Susuki 1) Toshiyuki 327-

Claims (1)

[Claims] 1 A semiconductor layer of a second conductive type formed on a first conductive type semiconductor substrate as a base, and connected to the substrate from the surfaces of the first conductive type semiconductor substrate and a second conductive type semiconductor substrate. A part of the first conductivity type region is used as a collector, and a part of the second conductivity type semiconductor layer is formed [7] 14'1811. In a semiconductor device in which a transistor is constructed using a high concentration region of a first conductivity type as an emitter, at least one conductivity type high concentration region θ) a second conductivity type is formed.
A second layer is formed on the conductive type semiconductor layer. ! A semiconductor device characterized in that a j1 type impurity is introduced.