JPS5883149U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5883149U
JPS5883149U JP1981179740U JP17974081U JPS5883149U JP S5883149 U JPS5883149 U JP S5883149U JP 1981179740 U JP1981179740 U JP 1981179740U JP 17974081 U JP17974081 U JP 17974081U JP S5883149 U JPS5883149 U JP S5883149U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
abstract
pellet
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981179740U
Other languages
English (en)
Other versions
JPS6334268Y2 (ja
Inventor
熊野 省治
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1981179740U priority Critical patent/JPS5883149U/ja
Publication of JPS5883149U publication Critical patent/JPS5883149U/ja
Application granted granted Critical
Publication of JPS6334268Y2 publication Critical patent/JPS6334268Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図及び第2図は、従来の半導体装置のペレットマウ
ント構体要部平面図、第3図は、この考案の実施例を示
す半導体装置のベレットマウント構体要部平面図、第4
図7第7図は、そのペレット表面処理を説明するための
ウェーハ断面図である。 2.3・・・・・・表面電極、4・・・・・・ペレット
、12゜13.14・・・・・・マーキング。

Claims (1)

    【実用新案登録請求の範囲】
  1. ペレットの表面電極上に、電極縁部より複数個半島状に
    延ばした絶縁被膜製のマーキングを設けたことを特徴と
    する半導体装置。
JP1981179740U 1981-11-30 1981-11-30 半導体装置 Granted JPS5883149U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981179740U JPS5883149U (ja) 1981-11-30 1981-11-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981179740U JPS5883149U (ja) 1981-11-30 1981-11-30 半導体装置

Publications (2)

Publication Number Publication Date
JPS5883149U true JPS5883149U (ja) 1983-06-06
JPS6334268Y2 JPS6334268Y2 (ja) 1988-09-12

Family

ID=29975706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981179740U Granted JPS5883149U (ja) 1981-11-30 1981-11-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS5883149U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010074499A (ja) * 2008-09-18 2010-04-02 Panasonic Electric Works Co Ltd リレー装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010074499A (ja) * 2008-09-18 2010-04-02 Panasonic Electric Works Co Ltd リレー装置

Also Published As

Publication number Publication date
JPS6334268Y2 (ja) 1988-09-12

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