JPS5864039A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5864039A
JPS5864039A JP56163938A JP16393881A JPS5864039A JP S5864039 A JPS5864039 A JP S5864039A JP 56163938 A JP56163938 A JP 56163938A JP 16393881 A JP16393881 A JP 16393881A JP S5864039 A JPS5864039 A JP S5864039A
Authority
JP
Japan
Prior art keywords
aluminum
film
alumina
bonding pad
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56163938A
Other languages
Japanese (ja)
Inventor
Koji Yamada
耕司 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP56163938A priority Critical patent/JPS5864039A/en
Publication of JPS5864039A publication Critical patent/JPS5864039A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To improve the reliability of a semiconductor device under high temperature and high moisture by altering part of an aluminum deposited film to alumina, thereby enabling to use an aluminum having high corrosion resistance for a bonding pad. CONSTITUTION:When the surface of aluminum is used as an anode in an anodic oxidation method and a voltage of approx. 35V is applied for 10min, a thick alumina 6 is grown. Then, the alumina 6 is removed with an alumina etchant. At this time, the surface 7 of corrosion resistant aluminum is exposed. Subsequently, aluminum 5 is selectively etched, thereby forming aluminum electrode, wirings and bonding pad. Thereafter, an oxidized film growing film, plasma nitrided film or their multilayer protective film is formed as a surface protective film 8 on the electrode, wirings and bonding pad of the aluminum 5. Then, the plasma nitrided film or oxidized film growing film of the bonding pad is removed by a plasma etching or the like. Thus, an aluminum film surface 7 which is hardly dissolved in water due to modification at the time of forming the alumina film is exposed on the surface.

Description

【発明の詳細な説明】 本発明はアルＲエクムを用い耐食性の高い電極構造を有
する半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having an electrode structure with high corrosion resistance using AlR Ecum.

従来、ＩＣ（集積回路）等に使用されているアル建を用
いた電極配線上の株面保義方法には、電極形成工程にお
いてアル建ニウム蒸着後配線及び電極パターンｔ−形成
し、酸化膜成長、プラズマ窃化瞑成長等及びそれらの多
層保Ｉｌ暎を形成する方法がある。とζろが実際にはペ
レット内の素子とボンディングワイヤーを接続するため
６ボンデイングバツド部を形成するため１表面保ｌｌ１
ｌＩを選択的に除去するので、ペレット表面ｔ−表面保
ＩＩ！ＩＫで保饅して４、ポンディングパッド部におい
ては配線や電極のアルンエクム表面が露出する。次に配
線や電極のポンディングパッド部のアルミニウムとボン
ディングワイヤーの一端とｔ＊続し、ボンディングワイ
ヤーの他端とリードフレームとを接続させる。次にペレ
ット及びボンディングワイヤーをモールド樹脂で封入す
る。ところが、ボンディングワイヤー及びモールド樹脂
との間隙を通ル、外気の水蒸気が侵入し、べＶットに形
成したポンディングパッド部のアルミニウムを腐食させ
る現象が発生する。そのポンディングパッドに用いてい
る高純度のアル＜＝ラムは外気の水蒸気に対し耐食性が
悪いため短時間でペレッを内のアルミニラムの配線とポ
ンディングパッドとの間のアルミニウムが腐食し、断線
すると言う欠点があった。Conventionally, in the method of preserving the surface of electrode wiring using aluminum alloy used in ICs (integrated circuits) etc., wiring and electrode patterns are formed after aluminum evaporation in the electrode formation process, and oxide film growth is performed. There are methods for forming multi-layered structures such as plasma irradiation, plasma growth, etc. and ζro are actually 6 bonding pads for connecting the elements inside the pellet and the bonding wires.
Since lI is selectively removed, the pellet surface t-surface retention II! After IK is applied, the surfaces of the wiring and electrodes are exposed at the bonding pad portion. Next, the aluminum of the bonding pad portion of the wiring or electrode is connected to one end of the bonding wire, and the other end of the bonding wire is connected to the lead frame. Next, the pellet and bonding wire are encapsulated with mold resin. However, a phenomenon occurs in which water vapor from the outside air enters through the gap between the bonding wire and the molding resin, corroding the aluminum of the bonding pad portion formed on the V. The high-purity aluminum used in the bonding pad has poor corrosion resistance against water vapor in the outside air, so the aluminum between the internal aluminum ram wiring and the bonding pad will corrode and break in a short time. There was a drawback.

本発明の目的は、外部から侵入する水蒸気によって電極
や配線の断線のない半導体装置の製造方法を提供するこ
とにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause disconnection of electrodes or wiring due to water vapor entering from the outside.

この発明は、ペレットの素子部を形成後高純度のアル１
＝ウムを蒸着した後、電極中配線形成工程以前に−１ア
ルミニウム表面を陽極酸化法を用いてアルミナ化し、ア
ルンナとアルミニウム界面近傍のアルずニウムを変質さ
せた後、アルミナを除去し１次いでアルミニウムの電極
配線及びポンディングパッドを形成した後、表面保護膜
である気相成長酸化暎、プラズマ窒化膜郷を形成し、ポ
ンディングパッド部の我面保ｓｉｘを除去し、形成され
たポンディングパッドの露出したアルミニウムの耐食性
を向上させる。In this invention, after forming the element part of the pellet, high-purity aluminum
= After evaporating aluminum and before the process of forming interconnects in the electrode, the -1 aluminum surface is aluminized using an anodizing method, altering the quality of the aluminum near the interface between the aluminum and the alumina, and then removing the alumina and then forming aluminum. After forming the electrode wiring and the bonding pad, a surface protective film of vapor phase growth oxide and plasma nitride film is formed, and the surface protection film of the bonding pad is removed. Improves the corrosion resistance of exposed aluminum.

本発明によれば、ペレットをモールド樹脂に封入後、モ
ールド樹脂を通シ浸入してくる外気の水蒸気によりポン
ディングパッド部のアルきニウムの腐食による回路配線
の断Ｓを防ぐことができる。According to the present invention, after the pellets are encapsulated in the mold resin, breakage of the circuit wiring due to corrosion of aluminum in the bonding pad portion due to water vapor from the outside air entering through the mold resin can be prevented.

次に、この発明を図面にもとづいて、より詳細に説明す
る。Next, the present invention will be explained in more detail based on the drawings.

まず、ＭＸ図に示すように、シリコン基板１上に必要な
トランジスタ等の素子２を不純物拡散等によって形成す
る。次に、シリコン基板１の表面上のフィールド酸化膜
３に、各素子毎にコンタクト窓４をあける。その表面に
蒸着法を用いてアルミニウム蒸着１１１５を形成する。First, as shown in the MX diagram, necessary elements 2 such as transistors are formed on a silicon substrate 1 by impurity diffusion or the like. Next, a contact window 4 is opened in the field oxide film 3 on the surface of the silicon substrate 1 for each element. An aluminum vapor deposit 1115 is formed on the surface using a vapor deposition method.

次に第２図に示すように、陽極酸化法によりアルミニウ
ムの表面をエチレングリコールとホウ酸アンモニウム水
溶液が１：３の混合液を電解液として用い、アルミニウ
ム表面を陽極とし約３５Ｖで１０分間電圧を印加すると
アルミニウムの表面は約２０００〜３０００Ａ稚度の膜
厚のアルばす６が成長する。同様にして２．５％シェウ
酸水溶液を用いて約１０Ｖで１０分印７１０しても同様
のアルミナ６が得られる。Next, as shown in Figure 2, the surface of the aluminum was subjected to anodization using a 1:3 mixture of ethylene glycol and ammonium borate as an electrolyte, and a voltage of approximately 35V was applied for 10 minutes using the aluminum surface as an anode. When this voltage is applied, an Albus 6 with a thickness of approximately 2000 to 3000 Å grows on the surface of the aluminum. Similarly, a similar alumina 6 can be obtained by applying a 10 minute mark 710 to about 10 V using a 2.5% schealic acid aqueous solution.

次に、＠３図において、７ツ酸、硫酸、純水の比率が１
：１０：１００で混合したアルミナエツチング液でその
アルミす６を除去する。この時、アルミナ６とア、ルミ
ニウム５界面近傍のアルミニウム５はアルミナエツチン
グ液及び水に対し溶けにくいアルミニウム材質に変質し
ており、耐食性アルミニウム表面７があられれる。次に
、フォトリングラフィ法を用いてアルミニウム５を選択
エツチングして、アルミニウムの電極や配線及びポンデ
ィングパッドを形成する。Next, in Figure @3, the ratio of heptonic acid, sulfuric acid, and pure water is 1.
The aluminum sulfur 6 was removed using an alumina etching solution mixed at a ratio of: 10:100. At this time, the aluminum 5 near the interface between the alumina 6 and the aluminum 5 has changed into an aluminum material that is difficult to dissolve in an alumina etching solution and water, and a corrosion-resistant aluminum surface 7 is formed. Next, the aluminum 5 is selectively etched using photolithography to form aluminum electrodes, wiring, and bonding pads.

次に、８４図に示すように、アルミニウム５による電極
や配線およびポンディングパッド上に妖面保［１１８と
しての酸化膜成長膜又はプラズマ窒化膜又はそれらの多
層保護膜を形成する。次に、第５図に示すように、ボン
デ４ングバッド部のアルミニウム５１−表面に出すため
にポンディングパッド部のプラズマ窒化膜又は酸化膜成
長膜をプラズマエツチング法及びフッ酸によるエツチン
グ等によ〕除去する。この結果、アルミナ膜形成時に変
質し水に溶けに〈〈なったアルミ膜面７が表面に出る。Next, as shown in FIG. 84, an oxide film growth film, a plasma nitride film, or a multilayer protection film thereof is formed as a mask 118 on the electrodes, wiring, and bonding pads made of aluminum 5. Next, as shown in FIG. 5, the plasma nitride film or oxide film grown on the bonding pad portion is exposed to the surface of the aluminum 51 on the bonding pad portion by plasma etching, hydrofluoric acid etching, etc. Remove. As a result, the aluminum film surface 7, which changed in quality during the alumina film formation and became soluble in water, appears on the surface.

この様にして、製造したウェハーをベレッタイズ工程で
個々のペレット１３に破断・分離した後。After the wafer manufactured in this manner is broken and separated into individual pellets 13 in a pelletizing process.

第６図に示すように、耐食性の高いポンディングパッド
９のアルミ表面にボンディングワイヤー１０の一端をつ
け、その反対側はリードフレーム１１に接続する。次に
モールド樹脂１２でペレット１３、ボンディングワイヤ
ー１０及びリードフレーム１１の先端部を封入する。As shown in FIG. 6, one end of a bonding wire 10 is attached to the aluminum surface of a highly corrosion-resistant bonding pad 9, and the other end is connected to a lead frame 11. Next, the pellet 13, the bonding wire 10, and the tip of the lead frame 11 are encapsulated with molding resin 12.

従来の製造方法によシ完成した集積回路製品は高温多−
湿下で故障することがあるため、加速試験を行ない破壊
させると、ボンディングワイヤーとモールド樹脂との間
隙を通り外気の水蒸気が浸入　　　゛しポンディングパ
ッド部のアルミニウムを溶解させることがある。この時
、本発明の製造方法によれば、アルミニウムのポンディ
ングパッド部の表面に腐食速度の遅いアルミ材質がある
ため、上記条件下で本アル電ニウム我面は溶解しない為
破壊に至る時間が長くなる。アルミニウム表面をアルミ
すにし、その界面近傍のアルミニウムの耐食性を高めた
後、アルミニウム配線のパターニングをし、酸化膜成長
、プラズマ窒化膜成長をする本発明の製造方法は、従来
方法である高純度のアルミニウムの蒸着膜を用いてアル
ミニウムの電極や配線のパターニングをし、酸化膜成長
、プラズマ窒化嘆成長をする製造方法に対し、モールド
樹脂封入後の高温多湿下で１．６〜２．０倍の鍔命を得
ることができる。尚、この発明によシボンディングパッ
ド部のアルミニウムとボンディングワイヤーの接着が弱
くなり、他の不要を発生させる現象は発生していないの
で、電気的特性上及び信頼性上は問題ない。Integrated circuit products completed using conventional manufacturing methods are exposed to high temperatures and high temperatures.
Since it may fail under humidity, if an accelerated test is performed to destroy it, water vapor from the outside air may enter through the gap between the bonding wire and the molding resin and dissolve the aluminum in the bonding pad. At this time, according to the manufacturing method of the present invention, since there is an aluminum material with a slow corrosion rate on the surface of the aluminum bonding pad, the aluminum surface does not melt under the above conditions, so it takes time for destruction to occur. become longer. The manufacturing method of the present invention, in which the aluminum surface is made into an aluminum slat, the corrosion resistance of the aluminum near the interface is increased, and then the aluminum wiring is patterned and oxide film growth and plasma nitride film growth are performed is different from the conventional method. Compared to the manufacturing method in which aluminum electrodes and wiring are patterned using a vapor-deposited aluminum film, followed by oxide film growth and plasma nitridation growth, the manufacturing process is 1.6 to 2.0 times faster under high temperature and humidity after encapsulation with mold resin. You can obtain Tsuba life. Incidentally, according to the present invention, the bond between the bonding wire and the aluminum in the bonding pad portion becomes weak, and no other unnecessary phenomenon has occurred, so there is no problem in terms of electrical characteristics and reliability.

なお１以上は本発明の一実施例を述べたが、アルミナと
アルミニウムとの界面近傍のアルミニウムの変質による
アルミニウムの耐食性を向上させる効果を明らかにする
ため、本発明ではアルミニウム表面をアルミナ化し１次
いてそのアルミナを除去したが、そのアルミナを除去せ
ず、アルミナの上に直接表面保＠膜を形成し、ポンディ
ングパッド部を形成し、ポンディングパッド部のみのア
ルミナを除去しても同様の効果が得られる。また、ポン
ディングパッド部以外のペレット表面は酸化成長膜、プ
ラズマ窒化膜及びその多層保＠−を用いて表面保＠を行
なったが、この外ポリイミド嘆等の保＠嗅も用いること
ができる。また、ポンディングパッド部以外は表面保護
膜を用いてペレットの表面保護を行なりたが、ポンディ
ングパッド部以外の表面保饅膜を必要としないペレット
にはアルミニウム狭面を一部アルミナ化しそのアルミナ
を除去した後電極や配線、ポンディングパッド部等のバ
ターニングをし、このようにして表面保鏝暎を形成しな
くとも同様の効果が得られる。また、蒸着材料として高
純度アルミニウムを用いたが、アルミニウムに他の金属
を含んだ、例えばＡｔ−Ｃｕ　、Ａｔ−８ｉ　、等の材
料を用イ’ｃ、アルよニウムをアル建す化して本同様の
効果か得られる。また、本発明に用いた製造方法は集積
回路以外のトランジスタ等の半導体装置にも充分応用で
色る。Although one embodiment of the present invention has been described above, in order to clarify the effect of improving the corrosion resistance of aluminum due to alteration of aluminum near the interface between alumina and aluminum, in the present invention, the aluminum surface is aluminized and primary However, the same result can be obtained even if the alumina is not removed, a surface protective film is formed directly on the alumina to form the bonding pad, and the alumina only on the bonding pad is removed. Effects can be obtained. Further, the surface of the pellet other than the bonding pad portion was protected using an oxide growth film, a plasma nitride film, and a multilayer film thereof, but other protection such as polyimide film may also be used. In addition, a surface protective film was used to protect the surface of the pellet except for the bonding pad area, but for pellets that do not require a surface protective film other than the bonding pad area, a part of the narrow aluminum surface is aluminized. After the alumina is removed, the electrodes, wiring, bonding pads, etc. are buttered, and the same effect can be obtained without forming surface protection trowels. In addition, although high-purity aluminum was used as the vapor deposition material, materials containing other metals in aluminum, such as At-Cu and At-8i, could also be used. A similar effect can be obtained. Further, the manufacturing method used in the present invention can be sufficiently applied to semiconductor devices such as transistors other than integrated circuits.

以上述べた様に本発明によれば、アルミニラム蒸着膜を
一部アルミ′すに変更することにより耐食性の高いアル
ミニウムをポンディングパッドに用いることができ、半
導体製品の高温多湿下の信頼性を向上させる効果がある
。As described above, according to the present invention, aluminum with high corrosion resistance can be used for bonding pads by partially replacing the aluminum evaporated film with aluminum, thereby improving the reliability of semiconductor products under high temperature and high humidity conditions. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第５図は本発明の一実施例の製造工程を順次
説明するための断面図、第６図は本発明の一実施例によ
り製造された製品の組立後の断面図である。 ｌ・・・・・・シリコン基板、２・・・・・・素子％３
・・・・・・フィールド酸化膜、４・・・・・・コンタ
クト窓、５・・・・・・アルミニウム蒸着＠％　６・・
・・・・アルミナ％　７・・・・・・耐食性アルミニウ
ム表面、８・・・・・・豪面保１ｕｌｌ、　９・・・・
・・ポンディングパッド、１０・・・・・・ボンディン
グワイヤー、１１・・・・・・ＩＪ　−ト７レーム、１
２・・・・・・モールド樹脂。 峯１面 ！ 染２回 ｖ−３田 第４図 椿タワ ￥ｔ′回 １６４1 to 5 are cross-sectional views for sequentially explaining the manufacturing process of an embodiment of the present invention, and FIG. 6 is a cross-sectional view of a product manufactured according to an embodiment of the present invention after assembly. l...Silicon substrate, 2...Element%3
...Field oxide film, 4...Contact window, 5...Aluminum vapor deposition @% 6...
...Alumina% 7...Corrosion-resistant aluminum surface, 8...Excellent surface protection 1ull, 9...
... Bonding pad, 10 ... Bonding wire, 11 ... IJ-7 frame, 1
2...Mold resin. Mine 1! 2nd v-3 field 4th camellia tower ￥t' times 164

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の一表面上にアル建ニウム被膜を形成したＬ
アルさニクム被暎の表面の一部をアルミナ化する工種と
、＃記アル建ニウムを用いて電極、配線、ポンディング
パッド等を形成する工程と、前記アル虐すを少なくとも
前記ポンディングパッドに相当する部分で除去する工程
とを含むこと１＊徴とする半導体装置の製造方法。L with an aluminum film formed on one surface of a semiconductor substrate
A process of converting a part of the surface of the aluminum alloy into alumina, a process of forming electrodes, wiring, bonding pads, etc. using aluminum alloy, and applying the aluminum alloy to at least the bonding pad. 1. A method for manufacturing a semiconductor device, comprising the step of removing a corresponding portion.
JP56163938A 1981-10-14 1981-10-14 Manufacture of semiconductor device Pending JPS5864039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56163938A JPS5864039A (en) 1981-10-14 1981-10-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56163938A JPS5864039A (en) 1981-10-14 1981-10-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5864039A true JPS5864039A (en) 1983-04-16

Family

ID=15783670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56163938A Pending JPS5864039A (en) 1981-10-14 1981-10-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5864039A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919864B2 (en) 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7919864B2 (en) 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit

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