JPS5861521U - Excessive input distortion prevention circuit - Google Patents

Excessive input distortion prevention circuit

Info

Publication number
JPS5861521U
JPS5861521U JP15684881U JP15684881U JPS5861521U JP S5861521 U JPS5861521 U JP S5861521U JP 15684881 U JP15684881 U JP 15684881U JP 15684881 U JP15684881 U JP 15684881U JP S5861521 U JPS5861521 U JP S5861521U
Authority
JP
Japan
Prior art keywords
terminal
circuit
excessive input
distortion
prevention circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15684881U
Other languages
Japanese (ja)
Inventor
明 稲田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP15684881U priority Critical patent/JPS5861521U/en
Publication of JPS5861521U publication Critical patent/JPS5861521U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の過大入力歪み防止回路の回路図、第２
図は同回路を説明する−ための図面である。 １．１′・・・入力信号端子、２・・・音声出力増幅回
路、３・・・ジャック、４・・・外部接続プラグ、５・
・・内蔵スピーカ、６・・・歪み抑制用回路、７・・・
外部′スピーカ。Figure 1 is a circuit diagram of the excessive input distortion prevention circuit of the present invention, Figure 2
The figure is a drawing for explaining the circuit. 1.1'...Input signal terminal, 2...Audio output amplification circuit, 3...Jack, 4...External connection plug, 5...
...Built-in speaker, 6...Distortion suppression circuit, 7...
External speaker.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 音声出力増幅回路と、該増幅回路の出力信号が印加され
ると共に外部接続プラグの一端子が接続される第１端子
と該第１端子に常時接続されており且つ前記プラグが挿
入されると第１端子から切断される第２端子と前記プラ
グの他端子が接続される第３端子とを有するジャックと
、・前記第２端子と接地間に接続される小型内蔵スピー
カと、前記第２端子と前記増幅回路の入力端子間の負帰
還路に接続され且つ互に逆極性で並列に接続されたダイ
オードを含む抑制用回路とを備え、前記内蔵スピーカ使
用時には前記歪み抑制用回路により過大入力信号による
増幅器の飽和歪みを抑制すると共に外部接続プラグ使用
時には歪み抑制用回路を切断することを特徴とする過大
入力歪み防止回路。　　′an audio output amplification circuit, a first terminal to which an output signal of the amplification circuit is applied and one terminal of an external connection plug is connected; a jack having a second terminal to be disconnected from one terminal and a third terminal to which the other terminal of the plug is connected; a small built-in speaker connected between the second terminal and ground; and a suppression circuit including diodes connected in parallel with opposite polarities and connected to a negative feedback path between input terminals of the amplifier circuit, and when the built-in speaker is used, the distortion suppression circuit prevents excessive input signals from occurring. An excessive input distortion prevention circuit characterized by suppressing saturation distortion of an amplifier and disconnecting a distortion suppression circuit when an external connection plug is used. ′
JP15684881U 1981-10-20 1981-10-20 Excessive input distortion prevention circuit Pending JPS5861521U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15684881U JPS5861521U (en) 1981-10-20 1981-10-20 Excessive input distortion prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15684881U JPS5861521U (en) 1981-10-20 1981-10-20 Excessive input distortion prevention circuit

Publications (1)

Publication Number Publication Date
JPS5861521U true JPS5861521U (en) 1983-04-25

Family

ID=29949378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15684881U Pending JPS5861521U (en) 1981-10-20 1981-10-20 Excessive input distortion prevention circuit

Country Status (1)

Country Link
JP (1) JPS5861521U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559195B2 (en) * 1972-06-09 1980-03-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559195B2 (en) * 1972-06-09 1980-03-08

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