JPS5853510B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device operating at high speed.

Despite their large power consumption, bipolar transistors have a large conversion conductance, high operating speed, and large drive capacity, so they are used in arithmetic parts, memory parts, and other areas that require particularly high-speed operation in semiconductor integrated circuits. It is used in interface parts that require large driving capacity.

The operating speed of a bipolar transistor is largely limited by its parasitic capacitance.

For example, in order to cause a predetermined potential change by applying an input signal to the base, it is necessary to charge (discharge) the parasitic capacitance of the base.

Therefore, the operating speed is limited by the parasitic capacitance of the base.

Similarly, when the collector potential changes, the collector capacitance limits the operating speed.

Various attempts have been made to reduce parasitic capacitance in order to increase the speed of bipolar transistors, and most of them have been improvements within the structure of individual transistors.

However, when a transistor structure is formed on a substrate, a capacitance is also formed between the transistor structure and the substrate.

In order to reduce this capacitance, it was generally thought that it would be sufficient to reduce the impurity density of the substrate.

However, in conventional transistors, the collector-substrate capacitance is often larger than the collector-base capacitance.

As an example of a bipolar transistor structure aimed at high-speed operation, 5ET (5 stepped
The structure of the Electrode Transistor will be explained with reference to FIG.

Polysilicon 7 is laminated on emitter region 5 and collector region 7, thereby successfully reducing the distance between emitter electrode 5' and base electrode 4' and reducing the areas of the base and collector.

Therefore, the base resistance, the base-collector capacitance, and the collector-substrate capacitance are reduced, and the operating speed is improved.

In the SET structure shown in Fig. 1, 1 is a substrate made of a p region, 2 is a collector made of a buried n+ region, with an impurity density of about 1018 to 1020 crfL-3, and 3 is an impurity density of 1014 to 1017 CIn, about -3. n area of
4 is a base region consisting of a p region with an impurity density of 1017~
5 is an emitter consisting of one region and has an impurity density of about 1020 to 1021 Cpl-3, 6 is an insulating layer, γ is doped polysilicon, and 2z4t.

5' is each electrode.

Each transistor is isolated in the p region.

Isolation is by Oxide and Po
Insulator isolation (1ysilicon) and SiO2 (1ysilicon) and SiO2
It is also possible to use ``soplanar'' or the like.

Using such a SET structure bipolar transistor,
N T shown in Figure 2, which is said to be capable of the highest speed operation.
L (Non-Threshold Logi c
) According to an experimental example in which a 15-stage ring oscillator was constructed by assembling a circuit, a propagation delay time of 85 picoseconds (PS) was measured (ISS1SSCC77FA, 1 TS
akai etall"A 100 psbipol
ar logic” pp 196-197).

As in this example, when the base resistance and base-collector capacitance can be reduced and high-speed operation can be performed, the electrical characteristics between the collector and the substrate become important.

In FIG. 2, VER is set to a value of about -i, tv, and the tag board is normally kept at the ground potential.

In order to reduce the collector-substrate capacitance, the impurity density of the substrate 1 is set to be low, for example, about 1014 to 0116 cm-3.

The lower the impurity density of the substrate, the lower the collector-substrate capacitance.

However, when the impurity density of the substrate becomes low, the width of the depletion layer extending from the collector to the substrate side becomes unable to change following the rapidly changing collector voltage.

When the change in depletion layer width lags behind the time change in voltage, the collector-to-substrate region no longer acts as a simple capacitor;
This means that a frequency-dependent conductance is inserted between the substrates in parallel with the capacitance (Tadahiro Inumi, "Tassonet" No. 1).
Proceedings of the 3rd Semiconductor Technical Seminar, pp. 91-114; see Section 2), which deteriorates the characteristics of transistors in high-speed operation.

In conventional transistors, the collector-to-substrate capacitance is often larger than the collector-base capacitance, and at high frequencies, changes in the depletion layer width no longer follow the time changes in the collector voltage, resulting in conductance.△Characteristics at high frequencies The deterioration is significant.

Deterioration of characteristics at high frequencies will be explained in more detail using a bipolar transistor having a buried collector region as an example.

The buried region is typically provided in a substrate of opposite conductivity type and forms a pn junction with the substrate.

In the operating state, this pn junction is reverse biased.
The potential of the substrate and the potential of the buried region are selected.

However, although the substrate potential is kept constant, the potential of the buried region is changed depending on the operating state.

As an example of a switching operation, the potential of the buried region changes between two predetermined potentials (on potential and off potential).

If the potential change is gradual, the width of the depletion layer extending from the buried region toward the substrate immediately changes in response to the potential change.

However, when the potential changes quickly, such as in high-speed switching, the width of the depletion layer cannot follow the potential changes, and the connection between the buried region and the substrate is no longer simply due to the capacitance due to the depletion layer. , a conductance component also occurs.

A numerical example using small signal approximation is described below based on a simple model.

The area of the n+ type buried region is 75×10”dt.
(corresponding to the collector area of a bipolar transistor made by the normal in-planar method), the thickness of the p-type substrate is 300 mm.
Assume that a reverse voltage of IV is applied between the buried region and the substrate as μm.

In this state, in terms of an equivalent circuit, it is considered that a voltage of 1.0 cm is applied to the series connection of the capacitance C due to the junction (depletion layer) and the resistance r due to the neutral region of the substrate.

Table I shows the values of C, r and rC time constants depending on the impurity density of the substrate.

In this case, if a sub-nanosecond switching operation is to be performed, the distance between the buried region and the substrate is approximately 11 to 1. IKΩ resistance (93μU.

The state is equivalent to a state in which a conductance of 930 μU is connected.

On the other hand, since the collector current flowing through the above-mentioned transistor is usually several hundred microamperes, the resistance of the transistor is approximately several ohms.

The conductance that appears between the buried region and the substrate can therefore be equal to or even greater than the conductance of the transistor itself, and the transistor carries a very heavy load.

This heavy load is frequency dependent, so at high frequencies it greatly reduces the gain of the transistor, severely limiting its operating speed.

As mentioned above, in the past, the problem between the collector and the substrate has not been much considered, and in high frequency transistors, the impurity concentration of the substrate is usually selected to be low so as not to increase the capacitance between the collector and the substrate.

However, when trying to reduce the capacitance between the collector and the board,
It will be understood from the above explanation that if the impurity density of the substrate is reduced, the contribution of the conductance component will increase.

If the impurity density of the substrate is increased in an attempt to reduce the contribution of conductance, the capacitance between the collector and the substrate will naturally increase and the frequency characteristics will deteriorate.

As described above, according to the conventional transistor structure, the high frequency characteristics of the transistor are largely controlled by the junction between the collector and the substrate.

The above explanation took bipolar transistors as an example, but
This deterioration of characteristics is not limited to bipolar transistors, but all transistors that have embedded electrodes whose potential changes during operation (including field effect transistors and static induction transistors). appears in

An object of the present invention is to provide a transistor that eliminates the above-mentioned drawbacks and a semiconductor integrated circuit device that operates at high speed using the transistor.

In the bipolar transistor according to one embodiment of the present invention, the capacitance between the collector and the substrate is set to be sufficiently small, and the depletion layer extending from the collector to the substrate side does not expand or contract and no conductance is generated, so that high-speed operation is possible. However, the characteristics do not deteriorate.

FIG. 3 shows a cross-sectional view of a bipolar transistor according to an embodiment of the present invention.

In this example, a p-type high resistance region 1' is interposed between a p+W high impurity density substrate 1 and an n+ type collector 2.

The impurity density and thickness of the p- region 11 are selected such that the depletion layer created by the diffusion potential of the n+p-junction completely reaches the p+ region 11.

For example, the material is Si and the impurity density is lX10'3cm.
', IXI (114 cm a.

In the case of 1 xi O"cm", in order to reach the depletion layer while maintaining zero bias between the substrate and the buried layer, the thickness of the high resistance layer is 11 μm and 3.7 μm, respectively.

Select 1.1 μm or less.

It may be thicker if the substrate and buried layer are reverse biased.

When this transistor is incorporated into a circuit configuration as shown in FIG. 2, the collector 2 is grounded via a resistor R1, and the emitter side is connected to a negative voltage power source.

Therefore, the collector 2 has a negative potential compared to the ground point.

For example, input A. When B does not enter, the collector potential changes to about OV, and when at least one of inputs A and B enters, the collector potential changes to about -0.5V.

Therefore, if the substrate is kept at the ground potential in this circuit configuration, the collector and substrate will be forward biased, so the depletion layer width will be 70° larger than the width due to the diffusion potential difference.
Therefore, the thickness of the p-layer needs to be set even thinner.

Of course, even with this circuit configuration, if the substrate is kept at the power supply potential, the voltage between the substrate and the collector will be biased in the reverse direction, so the depletion layer will expand further than the depletion layer caused by the diffusion potential.

Therefore, it is sufficient to make the p- layer thinner than the width of the depletion layer that expands due to the diffusion potential, or it may be made thicker considering the potential distribution in the operating state.

In short, it is sufficient that a depletion layer exists between the collector and the substrate in the intended operating region.

In this circuit configuration, it is advantageous to maintain the substrate at the power supply potential in order to further reduce characteristic deterioration due to the conductance f that occurs when the collector-substrate voltage changes at high speed.

In circuit configurations where the emitter side is grounded, it is more advantageous to keep the substrate at ground potential.

Changes in Collector Potential On the other hand, if the depletion layer extending from the collector to the substrate side reaches the p+ region and the depletion layer width cannot be changed, conductance will not appear because the depletion layer width change cannot follow the collector potential. No matter how quickly the collector potential changes, characteristic deterioration due to collector-substrate conductance does not appear.

Normally, the thickness of the n region 3 is about 1 to 2 μm, so the p
- If the thickness of the region 1' is set to 4 to 5 μm or more, the collector-substrate capacitance can be made much smaller than the collector-base capacitance.

In the transistor having the structure of the present invention, there is almost no deterioration in characteristics between the collector and the substrate.

Of course, this transistor can be used alone, but its effects are especially remarkable when used in integrated circuits.

If isolation between each transistor is performed using an insulator such as the IOP method or the in-planar method, the parasitic capacitance will be further reduced.

Of course, a structure in which the conductivity types are completely reversed may also be used.

If the NTL logic gate shown in FIG. 2 is constructed using bipolar transistors constructed as shown in FIG. 3, its high speed performance will be further emphasized and power consumption will be reduced.

Although not as fast as NTL, ECL (Bmitter Coupled Logic) shown in Figure 4 operates at the same high speed.
It is also effective to use a bipolar transistor having the structure shown in FIG.

In the ECL shown in FIG. 4, only the two transistors located in the center are affected by the characteristics between the collector and the substrate.

That is, in a transistor in which resistors Rc, R, etc. are connected between the power supply VOO and the collector, the collector potential changes during operation, so that an influence between the collector and the substrate appears.

CML (current mod
The operating principle is the same in the case of ``elogic''.

In such high-speed logic circuits, the use of bipolar transistors with a high-resistance layer interposed between the substrate and the collector further promotes high-speed performance.

The use of the transistor shown in Figure 3 is not limited to the circuit shown in Figure 4.
Of course, it can be used for any other circuit such as TTLf,r.

Bipolar transistors are used not only in the high-speed operation parts mentioned above, but also in interface parts with external circuits.

Regarding the input section, a single inverter must transmit the input signal to many gates included in the semiconductor integrated circuit or send clock pulses according to the input signal from the external circuit. , must drive the decoder that drives the bit line.

Therefore, the inverter that enters the input interface is required to have a very large driving capacity.

Also, in the interface of the output section, the external circuit is usually TTL (Transistor Transistor).
(torLogic) gate, a very large current of, for example, 1.6 mA is required for driving, and an inverter with a large driving capacity is also required.

MOSFET from an external circuit driven by a TTL gate
FIG. 5 shows an example of a human interface to a semiconductor integrated circuit composed of a static induction transistor (SIT: MOS type is also included).

The left side of the dotted line is an external TTL gate, and the part sandwiched between the dotted lines is an interface using two bipolar transistors.

The integrated circuit is to the right of the dotted line.

FIG. 6 shows an example of a circuit that sends clock pulses to an integrated circuit composed of MOS FETs and SITs.

A circuit that is driven by a TTL gate and sends a clock pulse is composed of three transistors.

FIG. 7 shows an example of an interface circuit for driving an external TTL gate from a MOS FET integrated circuit.

This is an example in which an external TTL is driven by one bipolar transistor.

In these circuits, it is effective to apply the structure of the present invention to electrode portions whose potential changes.

A structure in which a bipolar transistor is formed on a low impurity density layer on a high impurity density substrate as shown in FIG. 3 is very easy to apply to an SIT integrated circuit.

I2L (Integrated In)ection
FIG. 8 shows an example of a Logic type SIT integrated circuit.

In Figure 8a, the injector is bipolar and transistor.

The driver is an example of a junction type SIT, and in Figure 8, the injector is a MOS SIT, and the driver is a junction type SI.
This is an example of T.

In FIG. 8, the gate electrode of the MOS SIT is set to the same potential as its drain, but of course it may be set to the same potential as the source depending on the structure, or it may be provided with an independent power source.

8c and d are the same circuits as those in FIG. 8a and b, respectively.

In FIGS. 8a and 8b, two drains are shown in the driver transistor, and the remaining two drains are arranged in the direction t perpendicular to the plane of the paper.

In FIG. 8a, the n+ region 14 is the emitter of a lateral npn bipolar transistor, and the n+ region 13 is the collector and gate of the inverted SIT.

p+ region 1 is the source of the inverted SIT, p+ region 12,
12' is the drain of the inverted SIT.

p interposed between the collector/gate region 13 and the substrate 1
- Region 1' also serves as the channel of the inverted SIT and the base of the lateral bipolar transistor.

Note that the electrodes are omitted in FIG. 8a.

Figure 8, No. 6, is SiO□, St. N4. It shows an insulating layer such as At203 or a combination of a plurality of them.

The distance between p region 15 and n+ region 13 is set so that this region becomes a complete l-depletion layer due to the diffusion potential of the +p- junction.

Each impurity density is region 1: 1017 to 10
About 20cm-3, area 1': 1012-1016c
rn-3 degree, region 12: 1018~10"crn
'degree, area 13: 1016-1020crrL-3
Region 14: approximately 1017 to 10"cm', Region 15: approximately 1014 to 1017 crrL-3.

Only the insulating layer on the surface of region 15 is set thin (
For example, about 1000 people or less),
The gate electrode 16 controls the potential barrier height and width of the channel.

The role of the p-region 1' is similar to that in the configuration of FIG. 8a.

FIG. 9 shows an example of the logical configuration of an OR gate and a NOR gate which are a combination of a plurality of inverters shown in FIGS. 8a and 8c.

In FIG. 9, the conductivity type is completely reversed from that in FIG. 8.

The configuration is a combination of two 5ITL units with two drains and one 5ITL unit with one drain.

In this way, all logic gates can be constructed by combining a plurality of units shown in FIG. 8 through wire connections.

Integrating such a circuit and applying the present invention is effective in speeding up the operation.

Dynamic RAM (Ra
ndom Access Memory) can also be configured.

An example is shown in FIG. Junction type 5IT (p+ region 22
data is accumulated depending on whether or not charges are accumulated in the gate-drain capacitance of (forms the source, the n+ region 23 the gate, and the p+ region 1 the drain).

The source electrode 22'% of the SIT The emitter 24' of the lateral bipolar transistor is a word line, and the SIT
The drain of IT (and also the base of the bipolar transistor) is the bit line.

The potential of the bit line changes when data is written or read.

Therefore, if the high resistance region 26 (which may be n or p-) is interposed between the bit line region and the high impurity density region of the opposite conductivity type, such as the substrate 27, the static Since the capacitance is reduced and the conductance has almost no effect, higher-speed writing and reading can be performed.

The lateral bipolar transistor in FIG. 10 may be a static induction transistor or a field effect transistor.

FIG. 11 shows a two-man gate that combines a bipolar transistor and an SIT.

T7. T2 is a pnp bipolar transistor;
3. T4 is an n-channel junction type SIT.

T3 is a level setting 5 for setting a desired voltage value.
IT (see Japanese Patent Application No. 52-12327 "Semiconductor Integrated Circuit").

T4 is a multi-source SIT.
Another source is placed in the direction perpendicular to the page.

The extraction region of the buried collector of the pnp bipolar transistor is arranged in a direction perpendicular to the plane of the paper.

In this example, T3. A protrusion is provided on a part of the substrate that becomes the drain of T4.

This protrusion is intended to improve high-speed operation and high-frequency characteristics.

Depending on the intended use of the circuit, it is not always necessary to provide this protrusion.

If there is no input to A or B, the gate potential of T4 is VDD.
T4 is in a conductive state because it is close to , and if even one input is applied to A or B, T4 is cut off.

Figure 11 In this structure, the collector of the bipolar transistor and the drain of SIT are kept at a constant potential during operation, and the bipolar transistor T1 whose potential changes
．． Since a high resistance region is inserted between the emitter of T2 and the substrate, extremely high speed operation is possible.

A semiconductor memory corresponding to a charge-coupled memory cell that has a large capacity and can perform high-speed writing and reading is disclosed in Japanese Patent Application No. 52-18465 "Semiconductor Memory";
No. 2-20653 "Semiconductor storage device", patent application No. 1982-3
No. 5956 "Semiconductor memory", patent application No. 52-36304
No. ``Semiconductor Memory'' and Japanese Patent Application No. 52-37905 ``Semiconductor Memory.''

FIG. 12 shows an example in which the present invention has been applied to improve one example.

The part located on the right side of the figure is the memory array part.

In the figure, an n+ region 51 buried long in the direction perpendicular to the plane of the paper is a bit line, and an electrode 54 (metal or low resistance polysilicon) provided through an insulating layer such as SiO2 is a word line.

A bit line region 51 and a collector are provided on a high impurity density substrate 55.

Charges are accumulated near the surface of n- region 52 surrounded by p+ region 53.

The inflow and outflow of charges is caused by the influence of the p+ region 53.
This is done via a potential barrier in region 52.

As an inverter in an interface section that drives a decoder in a memory array having such a configuration, a bipolar transistor is configured as shown on the left side of the figure to form an extremely high-speed semiconductor memory.

Of course, the structural example of a memory cell having such a configuration is not limited to this.

It can be applied to all the structures shown in the prior inventions.

Of course, the conductivity type can be reversed, and nonvolatile memory can also be created.

Up until now, the present invention has been explained mainly using bipolar transistors as an example, but the present invention is applicable not only to bipolar transistors but also to static induction transistors and field effect transistors (both junction type, insulated gate i Schottky transistors). (including types).

An example of a static induction transistor is shown in FIG.

High-speed operation is improved by providing a high resistance region 66 between the high impurity density substrate 65 and the buried drain region 63.

The configuration of FIG. 13 can also be used as an inverted SIT.

That is, the n+ regions 63 and 61 may be used as a source and the drain, respectively, and the p+ agate region 64 may be provided close to the source 63.

FIG. 14 shows a structural example in which the present invention is applied to MO8IT.

In a MOSFET, one of the sources 71, 7F or the drains 73, 73' is kept at a constant potential (ground potential or power supply potential), and the potential of the other electrode changes as the operating state changes.

At this time, the large capacitance between the source and the substrate or between the drain and the substrate was one of the factors that limited the speed of MOSFETs.

Examples of structures that reduce capacitance and do not generate conductance during high-speed operation are shown in FIGS. 14a and 14b.

A is an example of a single-layer structure, and b is an example of a "" structure.

The impurity density and thickness of the high resistance region between the source 71 or the drain 73, the electrode whose voltage fluctuates (the drain 73 in FIG. 14a) and the substrate 75, are such that it always forms a depletion layer in the main operating region. Set.

Figure 14 shows an example in which a high resistance region 72' is provided, and the impurity density and dimensions of 7z are such that a depletion layer exists between the source or drain and the substrate where the voltage changes, but a depletion layer exists between the source and drain. Set so that no punch-through current flows.

FIG. 15 shows an example in which the present invention is applied to MO8SIT.

81 and 83 are the source and drain, respectively.

Assuming that the drain 83 changes in voltage, the impurity density and thickness of the n region 82 between the n+ type drain region 83 and the p+ type substrate 85 are selected so that a depletion layer is formed between the drain and the substrate in the operating state.

The embodiments described above are specific examples of the present invention, and the present invention is not limited to these.

For example, it goes without saying that the conductivity type may be completely reversed, and MO8SIT.

It may also be used in a suitable combination of MOSFETs and the like.

When insulator separation such as an in-planar method is used, the conductivity type of the high resistance region may be the same as that of the buried region, or may be an intrinsic type.

The high resistance region may be provided over the entire surface of the substrate, or may be provided only between the substrate and the buried region.

In addition, in the case of bipolar transistors used in interfaces, etc., which require not only high-speed operation but also high driving ability, it is necessary to connect a high-resistance layer under the buried collector region. There is no need to provide a conductive type low resistance region.

In addition, a semiconductor device in which the SIT is replaced with a bipolar transistor in which the base region is almost or completely pinched off and punched through (Japanese Patent Application No. 52-15
No. 880 "Semiconductor integrated circuit" and patent application 1732-1983
It is also effective to apply the present invention to (see No. 7 "Semiconductor Integrated Circuits").

Embodiments of the present invention can be manufactured using conventionally known crystal growth techniques (including selective growth), microfabrication techniques, selective diffusion, selective etching, ion implantation techniques, and the like.

The structure that includes a low resistance region of the opposite conductivity type under the buried electrode via a high resistance layer improves the high speed performance of each transistor, and at the same time allows bipolar transistors, FETs, and SITs to be integrated in the same semiconductor chip. Facilitates integration.

It is easier to freely combine SIT, which has high input impedance, direct connection type circuits, and operates at low power consumption and high speed, and bipolar transistor, which consumes large amount of power, but operates at high speed and has large drive capacity, on the same semiconductor chip. It is easy to perform and can perform a wide variety of operations at high speed.

In addition, bipolar transistors and FBs exhibiting constant current characteristics
The flexible combination of T and SIT exhibiting constant voltage characteristics also increases the degree of freedom in circuit design and has high industrial value.

In addition, a semiconductor integrated circuit that combines SIT and bipolar transistors is advantageous in that it is possible to configure a bipolar transistor with high speed and large drive capacity in the interface part of an SIT integrated circuit within the same semiconductor chip without introducing any special process. The value of the invention is particularly high for circuits.

[Brief explanation of the drawing]

Fig. 1 is an example of a cross-sectional structure of a high-speed operation bipolar transistor, Fig. 2 is an NTL basic unit gate, Fig. 3 is an example of a cross-sectional structure of the present invention, Fig. 4 is an example of a NOR/OR gate structure, and Fig. 5 is an interface. Circuit example, Fig. 6 is a clock circuit example, Fig. 7 is an interface circuit example, Fig. 8 a to d is an IL type SIT inverter configuration example, and Fig. 9 is a basic logic circuit configuration f.
Figures 10a and 10b show an example of the cross-sectional structure and configuration of a dynamic RAM cell, Figures 11a and 11b show an example of a two-person NOR gate that combines a bipolar transistor and SIT, and Figure 12 shows an example of a memory array structure. Figures 13 to 15
The figures show one specific example of the present invention; FIG. 13 shows a junction type static induction transistor, FIG. 14 shows a MOS FET, and FIG. 15 shows a MOS SIT.

Claims (1)

[Claims] 1. In a transistor in which one of two main electrode regions through which current flows is a buried region, a high resistance region is interposed between the buried electrode region and a high impurity density substrate of an opposite conductivity type, and the high resistance region is 1. A semiconductor device comprising at least a portion of a transistor whose impurity density and various dimensions are selected so that the region becomes a depletion layer.