JPS5842335A - Full duplex data transmission system - Google Patents

Abstract

PURPOSE:To realize full duplex data transmission, by multiplexly modurating data and clock signals issued from a master device and transmitting them as current change signals, and making a subdevice receive the signals and compulsively the output of the master device to a loaded state with the transmission data. CONSTITUTION:In a master device ME, a clock pulse CLK from an oscillator OSC, a synchronizing signal SYN obtained from the count of the CLK, and a serial data signal DAT1 from a selector SEL1 are multiplexly modulated at a modulator MOD and applied to an operational amplifier OP. The output is inputted to transistors (TRs) Q1, Q2, to flow an output current to lines L1 and L2. In a subdevice SE, a transmission data signal SD2 turns on a TRQ3, which bridges over the lines L1 and L2, and the output current of the master device ME becomes compulsively loaded to change a control voltage of a constant current circuit of the master device. This change is detected at comparators CP1, CP2 as reception data, and the reception at the subdevice is detected by comparing a voltage across a resistor R4 with a reference voltage at a comparator CP3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a full-duplex data transmission system that simultaneously performs bidirectional data transmission using the same line with a simple configuration.

Conventional full-duplex data transmission systems perform two-way transmission using frequency band division or time division. Frequency band division requires expensive F-wave equipment and requires complicated frequency conversion. However, when using time division, bidirectional transmission cannot be performed completely simultaneously, and data transmission lacks immediacy. It had some disadvantages such as:

The present invention has the purpose of fundamentally solving the drawbacks of the conventional system, and the transmission from the main device to the sub device is performed by using a multiplexed signal of clock pulses, synchronization signals, and data signals. Controls the constant voltage rIlt voltage circuit, uses the output of the output as a transmission signal, and forces the output of the main device based on the transmission letter from the sub device to the main device and the transmission data signal on the sub device side. This is an extremely effective method that detects that the control voltage of the constant current or constant voltage circuit on the main device side changes according to the load condition, and thereby obtains the transmission data signal from the 11 devices. It provides a full-duplex data transmission method.

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram when a constant current circuit is used, and the main device MΣ includes an operational amplifier OP1 transistor Qi
A current stabilizing circuit consisting of XQm and resistors R1 to Rm is provided, and is driven by the output of an operational amplifier aop,
The transistors QL%QI operate in the linear region in a complementary manner, and the resistors *R1,l.

The output current is sent from the connection point of the line, ,L
The change in output current that circulates through the resistor R.

By detecting the terminal voltage of the transistor QCsQ! and applying it to the inverting input of the operational amplifier OP, the transistor QCsQ! The control voltage applied to the base of the output current is changed in a direction that suppresses changes in the output current, and a constant current output is sent to the narrow paths L1 and Ll.

Additionally, comparators CPi and cp are provided to compare the reference voltages +Vr and -Vr with the control voltage, thereby making it possible to detect a drop in the control voltage.

To avoid this, if a multiplexed signal with a double current is applied to the non-inverting input of the operational amplifier OP, a double current output tfI with the same waveform as this one can be obtained.
It is sent to the lines L1 and Ll, and the resistor 1 of the sub-device sg
A terminal voltage flowing through 1Ri and having the same waveform as the multiplexed signal appears at resistor 54.

This terminal voltage is applied to both inputs of the comparator CP via capacitors CI and CI, and the output current is rectified by diodes D1 to D, smoothed by capacitor Cs, and resistor R@ to When compared at the comparator CP- with the reference voltage applied through R1, a multiplexed signal is obtained as the output of the comparator CP-.

On the other hand, on the side of the sub-device 8, a low resistance value O resistor R-
A series circuit of and transistor Qs is connected,
When the transistor Q1 turns on/off in response to the transmission data signal gDs on the side of the sub-device BE, the diode D is turned off by the resistor.
1 to D4, the output current becomes a forced load state.

Then, although the output current does not change, the control voltage of the constant current circuit changes in the direction of decreasing, and the deviation is detected by the comparators CP1 and CF2, and becomes the received data signal wing D1 via the Non gate Ga.

In addition, the multiplexed signal on the main device ME side is a tortoise signal obtained by a modulator MOD that performs pulse phase modulation.
In this case, the clock pulse C from the oscillating isogc
LK, the clock pulse CLK is extracted by the color CT1 that counts this, and the data signal D is converted into a serial signal by the selector BNLI, which receives address designation by the 9 synchronization signal SYN and the count output of the color/receiver 0 M. 〒1 is multiplexed and modulated by the modulator MOD, becomes a multiplexed signal, and is applied to the non-inverting input of the operational amplifier OP.

On the other hand, the received serial data signal D from OR game) G
AT is given to the latch circuit LATI including a selector that operates according to the address designation, and is distributed according to the address designation by the count output of the counter CT. They are held individually in synchronization with the clock pulse CLK, and become received data signals RD1@1 to n-2.

For this reason, the transmission data signals 8D1.1 to 8D1 on the main device ME side
n-1 is the serial data signal DA by the selector 8ELl.
After T, the synchronization signal sYN from the clock pulse CLK and the count output Q of the counter CT
In addition, the multiplexed signal and signal are transmitted as output current changes of the current stabilizing circuit, and are also output by the demodulator DEM of the sub-device 8E to the lock pulse CLK, synchronization signal 8YN, and serial data signal D whip 1. The lyrics are written.

Synchronous signal 8 while outputting the adjuster DEM! N is empty/ri CT
, to the clear input CL of the clock pulse CLK
is given to the color/reverse CT and the input input CI, and after being reset by the synchronizing signal -N, the counter C
Since T counts the clock pulse CLIC, a b count output is obtained from the counter CT with the synchronization signal 11YN as a reference, and this is given to the latch circuit LATm as an address designation, and at the same time, the clock pulse via the inverter IN is output. CLK and serial data signal D
When AT is applied to the latch circuit LATm, the selector in the latch circuit LAT distributes the serial data Djk'r* according to the address specification, and the holding operation in synchronization with the clock pulse CLIC is performed by the latch circuit L. The serial data signal DA is
``rl becomes the received data signal RDy·1 to n-1.

In addition, the transmission data signal BDs・1 to n− on the side of the secondary device 8E
2 is sequentially and repeatedly selected by the selector 8ELmK in accordance with the address specification by the counter CTI, and becomes the serial data signal DAT, and in order to control the transistor Q3, the current on the main device ME side is stabilized accordingly. The control voltage of the circuit decreases, and whether the output current waveform at this time is positive or negative, the comparator CP1t detects this, and the serial data signal D
AT is obtained.゛Figure 2 shows the modulator MOD and demodulator D in Figure 1.
This is a block diagram showing the configuration of EM, and 1 transformer MOD has a NAND gate G1 and an exclusive OR (hereinafter referred to as EXOR).
Gate G! , Glq Inverter IN and flip-flop circuit (hereinafter referred to as FFC) FFI, FFm are configured, and demodulator DEN is FFC-FF, , gxO
R gate G4 and pulse generation such as a monostable multivibrator that generates pulses of a predetermined width @ PG, PC,
It operates as shown in FIG. 3, which shows the waveforms of each part as a timing chart.

That is, as shown in Fig. 1, since the clock pulse CLK is inputted by the CTI and the synchronization signal 8YN is obtained from the count output Qe, the clock pulse CLK (&
) and the synchronization signal 87N(b) are as shown in FIG.
1 to n-1, color/re CTI count output Q1 to Q
The rounding, serial data signal Dm τ1 (C), which is sequentially and repeatedly selected by the selector L1 of the selector 8 according to the clock pulse CLK (a), and the crotter pulse CLK (&) and synchronization signal syN>)
Based on this, the output (d) of the NAND gate 01 is obtained, which is directly given to the clock input CI of FFC-FF1, and is also inverted via the inverter IN.
After that, it is applied to the clock input CK of FFC-FF.

Then, FFC-FF repeats setting and resetting according to the rise of the inverted output (・)O, generates an output (f) and an inverted output (g), and EXORs the same output (b).
The serial data signal DATt(e
) and the inverted output (g), an output (h) is sent out from the IIO gate q-, and this is given to the data output of FFC-FF1.

ζot, FFC-FF, Fi, generates an inverted output (j) in response to the D-type operation using the output (d) as a clock pulse, and based on the same output (j) and output (f), the EXOR gate G output), which becomes a multiplexed signal.

The multiplexed signal (transfer) is transmitted through the D-type operation FFC of the demodulator DICM.
・The clock input CK of the FF is provided through the EYOR game) G4 and the pulse generator PC1 which generates a pulse having a pulse width of 1% with respect to the period width T of the clock pulse. A feedback output is given, and by this feedback action, the output (a) of FFe-FF is demodulated into the serial data signal DATI and the multiplexed signal carrier to obtain the output of EXOR gate G4). , the rise of this pulse generator P0
1 is driven, an inverted output (n) is obtained, and depending on the rise of this and the status of the multiplexed signal carrier, the output (2) is constant, and this becomes the demodulated clock pulse CLK.

In addition, in response to the fall of the inverted output (n), the pulse generator PG■ which generates a pulse whose period is equal to/(pulse width) T of the clock pulse cLK (11) is driven, and its inverted output is driven. middle) becomes the demodulated synchronization signal 8YN.

Therefore, as shown in FIG. 1, the serial data signal DAT1
If the clock signal RD is distributed to the clock signal RD and held in synchronization with the clock CLK, each individual received data signal RD,
As is clear from FIG. 3, the leading edge of the demodulated serial data signal nATt (A and the leading edge of the demodulated clock pulse CL K (n') are occurring at the same time, so that the output of the inverter INI (rising at ψ), which inverts the clock pulse CL K (n), is maintained for the purpose of keeping the serial data signal D whip μ stable. It is used as a strobe signal for latch circuit LATI.

In addition, in the main device MAL@, similar m- is used to invert by invert/INt,
K is used as a strobe signal for the latch circuit L block 1.

In addition, as is clear from Figure 3, clock pulse x
10″ and n# of cLK(a) are synchronization signals!IYN(b
), this timing cannot be used for data transmission, and input/output #0# and “n” of selector 8ELl and latch circuit LATm are not used, and main unit iiMK side clock pulse C
IJ(a) Ill device [8EIl・Clock pulse C
Due to the phase relationship with LK (nl), the input "02 to 1n-2" of the selector 81CL and the output m1 of the latch circuit LATI
# to "n-1" correspond to each other, and in order to avoid the influence on the synchronization signal component in one multiplexed signal (b), the input "n 1 # S# n" of the selector 8EL is
Correspondingly, the outputs "0# and 'n" of the latch circuit LATI are not used.

FIG. 4 is a main circuit diagram when a constant voltage circuit is used. Similarly to FIG. 1, the operational amplifier OP1 transistor Qs,
Qm and resistors R1 and Rfi are provided, but the connection point voltage of resistors R1 and R1 is applied to the inverting input of operational amplifier OP, and these constitute a constant voltage circuit.
If the transistor Qs shown in Fig. 1 is forcibly placed between l and L1 in a loaded state, the control voltages applied to the paces of the transistors Ql and Ql will be concentrated in the upward direction, and the multiplexed signal waveforms of this and t& will be correct. or negative, depending on whether
Since the comparator CP1t or CPS generates a detection force, if this is extracted through the OR gate (Gb), it can be used in the same manner as the constant current circuit shown in FIG.

Therefore, bidirectional and completely simultaneous transmission can be achieved with a simple configuration without using a frequency converter, a frequency converter, etc., and it is possible to easily obtain instantaneous data transmission as well as a reduction in the cost of the device.

As for the modulation format, other modulation formats may be used as long as they can be transmitted by pulse signals, and it is the same even if a single polarity is used as the output current or voltage. Easy to use switching elements.

Further, as long as it is a constant current or constant voltage circuit and has similar functions, nine selections can be made depending on the conditions, and a plurality of sub devices 8E may be used, and the present invention can be freely modified in various ways. .

As is clear from the above description, according to the present invention, bidirectional data transmission with complete simultaneity can be realized with a simple and inexpensive configuration, and remarkable effects can be obtained in data transmission for various purposes.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, in which Fig. 1 is a block diagram of a case in which a constant current circuit is used, Fig. 2 is a block diagram of the modulator and demodulator in Fig. 1, and Fig. 3 is a block diagram of the modulator and demodulator in Fig. 2. Figure 4 is a circuit diagram of the main parts when a constant voltage circuit is used. CLK...clock pulse, BYNII@...synchronization signal, DATI, Dmuchimaro...data signal, MOD
...Modulator, DIM*...Demodulator, c'rl, c
〒鵞・・・Counter, Qp * s 11 & operational amplifier, cpl~CP, ・・・Comparator, Q1~Q3...
...Transistor, R1 to R9...Resistor, D1~
DIΦ・Fist-diode, C1~Cs@... Capacitor, Ml... Main device, 81... Sub device. Patent Applicant Tadao Totsuka' Agent Masaki Yamakawa (and one other person)
91, Indication of the case 1982 Patent Application No. 139775 2, Name of the invention Full-duplex data transmission method 3, Person making the amendment Relationship with the case Patent Number of inventions increased by applicant's amendment... Correct C shear-r small d1ge7 θ~j. (2) “KYORJ” on page 10, line 9 of the same book
Correct with J. (3) Revise Figure 1 from the attached sheet. that's all

Claims (2)

[Claims] (1) A clock pulse, a synchronization signal, and a data signal are multiplexed into a multiplexed signal, and the same waveform as the multiplexed signal of the current stabilization circuit controlled by the armpit multiplexing signal is generated. The output current shown is sent from the main device, and a! ! At the same time, the output current is demodulated into the tarotsuta pulse, a synchronization signal, and a data signal, and the output current is forcibly put into a load state by the transmission data signal from the sub-device, and the output current is put into the load state in the main device. The transmission data signal expression on the rigid device side is caused by a change in the control voltage of the current stabilizing circuit in response to the change in the control voltage of the current stabilizing circuit. (2) A clock pulse, a synchronization signal, and a data signal are made into a multiplexed signal according to the multiplexing cost, and an output voltage having the same waveform as the multiplexed signal is sent from the main device, and the secondary device outputs the output voltage. The current is demodulated into the clock pulse, synchronization signal and data signal, and the transmission data of
A signal is used to forcibly set the pre-distribution output current to a load state, and in the main device, the control voltage of the voltage stabilizing circuit changes in accordance with the load state.