JPS5836512B2 - 半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線 - Google Patents

半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線

Info

Publication number
JPS5836512B2
JPS5836512B2 JP50036536A JP3653675A JPS5836512B2 JP S5836512 B2 JPS5836512 B2 JP S5836512B2 JP 50036536 A JP50036536 A JP 50036536A JP 3653675 A JP3653675 A JP 3653675A JP S5836512 B2 JPS5836512 B2 JP S5836512B2
Authority
JP
Japan
Prior art keywords
semiconductor memory
memory chips
chip
wiring
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50036536A
Other languages
English (en)
Japanese (ja)
Other versions
JPS50131493A (https=
Inventor
ザプナロウ ミヒアイル
ミツテラ− ル−ドルフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPS50131493A publication Critical patent/JPS50131493A/ja
Publication of JPS5836512B2 publication Critical patent/JPS5836512B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
JP50036536A 1974-03-28 1975-03-26 半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線 Expired JPS5836512B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19742415047 DE2415047B2 (de) 1974-03-28 1974-03-28 Multichip-verdrahtung mit anschlussflaechenkonfigurationen zur kontaktierung von vier gleichen halbleiterspeicher-chips
DE2415047 1974-03-28

Publications (2)

Publication Number Publication Date
JPS50131493A JPS50131493A (https=) 1975-10-17
JPS5836512B2 true JPS5836512B2 (ja) 1983-08-09

Family

ID=5911463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50036536A Expired JPS5836512B2 (ja) 1974-03-28 1975-03-26 半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線

Country Status (8)

Country Link
JP (1) JPS5836512B2 (https=)
BE (1) BE827367A (https=)
DE (1) DE2415047B2 (https=)
FR (1) FR2266305B1 (https=)
GB (1) GB1464080A (https=)
IT (1) IT1034529B (https=)
NL (1) NL7502773A (https=)
SE (1) SE7503369L (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0279123U (https=) * 1988-12-02 1990-06-18
JPH02285910A (ja) * 1989-04-26 1990-11-26 Seijiro Isoi 鳥休止防止具
JPH052533U (ja) * 1991-02-25 1993-01-14 マサル工業株式会社 電線保護カバー

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3033900C3 (de) * 1980-09-09 1994-12-15 Siemens Ag Gehäuseloses Schaltungsmodul und Verfahren zu seiner Herstellung
DE3123620A1 (de) * 1981-06-13 1983-01-05 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Anordnung zum verbinden eines speichers mit einer steuereinrichtung
JPS57207356A (en) * 1981-06-15 1982-12-20 Fujitsu Ltd Semiconductor device
GB2312562B (en) * 1996-04-26 2000-05-17 Appliance Control Technology E A method of interconnecting wiring with a pcb

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0279123U (https=) * 1988-12-02 1990-06-18
JPH02285910A (ja) * 1989-04-26 1990-11-26 Seijiro Isoi 鳥休止防止具
JPH052533U (ja) * 1991-02-25 1993-01-14 マサル工業株式会社 電線保護カバー

Also Published As

Publication number Publication date
DE2415047C3 (https=) 1978-09-21
NL7502773A (nl) 1975-09-30
IT1034529B (it) 1979-10-10
DE2415047B2 (de) 1978-02-02
FR2266305B1 (https=) 1978-02-24
JPS50131493A (https=) 1975-10-17
SE7503369L (https=) 1975-09-29
DE2415047A1 (de) 1975-10-16
BE827367A (fr) 1975-07-16
GB1464080A (en) 1977-02-09
FR2266305A1 (https=) 1975-10-24

Similar Documents

Publication Publication Date Title
US5780925A (en) Lead frame package for electronic devices
US5448511A (en) Memory stack with an integrated interconnect and mounting structure
US5426566A (en) Multichip integrated circuit packages and systems
JP2870530B1 (ja) スタックモジュール用インターポーザとスタックモジュール
US5473196A (en) Semiconductor memory component comprising stacked memory modules
US4972253A (en) Programmable ceramic high performance custom package
US6043559A (en) Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses
JP2603636B2 (ja) 半導体装置
US4942453A (en) IC package
US5787575A (en) Method for plating a bond finger of an intergrated circuit package
JPS5836512B2 (ja) 半導体メモリチツプの接続のための端子面配列を持つマルチチツプ配線
JPS61278160A (ja) 半導体集積回路用接続装置
JP2765571B2 (ja) マルチチップモジュール
JP2581532B2 (ja) 半導体装置
JPH04196253A (ja) 半導体装置用パッケージ
JP2865102B2 (ja) マルチチップモジュール
JPH08186227A (ja) 半導体装置及び電子装置
JP2706699B2 (ja) 半導体モジュール
JPS58184735A (ja) 集積回路チツプ
JP2000068405A (ja) 半導体装置およびその製造方法
JP2713876B2 (ja) 半導体装置
JP2555991B2 (ja) パッケージ
JPH023957A (ja) 半導体集積回路
JP3064379U (ja) 集積回路パッケ―ジ立体組立構造
JPS62133743A (ja) 多層配線基板