JPS5833752A - デイジタル信号処理装置におけるル−プ演算制御方式 - Google Patents

デイジタル信号処理装置におけるル−プ演算制御方式

Info

Publication number
JPS5833752A
JPS5833752A JP56132067A JP13206781A JPS5833752A JP S5833752 A JPS5833752 A JP S5833752A JP 56132067 A JP56132067 A JP 56132067A JP 13206781 A JP13206781 A JP 13206781A JP S5833752 A JPS5833752 A JP S5833752A
Authority
JP
Japan
Prior art keywords
loop
circuit
ram
control method
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56132067A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6346871B2 (enrdf_load_stackoverflow
Inventor
Mitsuo Shimada
島田　光夫
Toshitaka Tsuda
俊隆 津田
Yuichi Miwa
裕一 三輪
Hiroaki Imaide
広明 今出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56132067A priority Critical patent/JPS5833752A/ja
Publication of JPS5833752A publication Critical patent/JPS5833752A/ja
Publication of JPS6346871B2 publication Critical patent/JPS6346871B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
JP56132067A 1981-08-25 1981-08-25 デイジタル信号処理装置におけるル−プ演算制御方式 Granted JPS5833752A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56132067A JPS5833752A (ja) 1981-08-25 1981-08-25 デイジタル信号処理装置におけるル−プ演算制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56132067A JPS5833752A (ja) 1981-08-25 1981-08-25 デイジタル信号処理装置におけるル−プ演算制御方式

Publications (2)

Publication Number Publication Date
JPS5833752A true JPS5833752A (ja) 1983-02-28
JPS6346871B2 JPS6346871B2 (enrdf_load_stackoverflow) 1988-09-19

Family

ID=15072734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56132067A Granted JPS5833752A (ja) 1981-08-25 1981-08-25 デイジタル信号処理装置におけるル−プ演算制御方式

Country Status (1)

Country Link
JP (1) JPS5833752A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS6346871B2 (enrdf_load_stackoverflow) 1988-09-19

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