JPS5832423A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS5832423A
JPS5832423A JP56130331A JP13033181A JPS5832423A JP S5832423 A JPS5832423 A JP S5832423A JP 56130331 A JP56130331 A JP 56130331A JP 13033181 A JP13033181 A JP 13033181A JP S5832423 A JPS5832423 A JP S5832423A
Authority
JP
Japan
Prior art keywords
leads
fins
semiconductor chip
cooling fins
thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56130331A
Other languages
English (en)
Inventor
Kazutoyo Narita
成田　一豊
Tadashi Sakagami
阪上　正
Noboru Kawasaki
昇 川崎
Keiichi Kuniya
国谷　啓一
Mitsunari Kamata
鎌田　充也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56130331A priority Critical patent/JPS5832423A/ja
Publication of JPS5832423A publication Critical patent/JPS5832423A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は銅マトリクス中に炭素繊維を埋設した複合材（
以下、複合材と略記）を用いた半導体装置に係り、特に
半導体チップと冷却フィ／、半導体チップとリード間鑞
材のせん断応力軽減と半導体チップ接合部での発生熱を
良好に放熱するに好適な半導体装置に関する。
従来の半導体装置は第１図に示すように、半導体チップ
収納用凹部加工を施した冷却フィン２に、半導体チップ
１、リード３をそれぞれ鑞材４ａ。
４ｂを介して接続するか、第２図のように半導体チップ
１と冷却フィン２の間にタングステン、モリブデン等の
比較的半導体チップ１に熱膨張係数の近い熱応力緩和材
５を用いて鑞材４Ｃで接続し、ンリコーンゴム６を充填
する構造となっていた。
しかし前者において、冷却フィン２側への放熱性は比較
的良いがリード３側への放熱性が悪く、また半導体チッ
プ１と冷却フィン２、リード３との熱膨張、係数差が大
きいため、鑞材への熱応力の影響が大きいこと、後者に
おいて、応力緩和材５により半導体チップ１と冷却フィ
シ２間の熱応力は緩和されるが放熱性が低下（＝熱抵抗
が大）し、更に製品コストが高くなるという欠点があっ
た。
本発明の目的は半導体チップでの発熱を冷却フィンおよ
びリード側に有効に放熱するとともに、鑞材部への熱応
力を緩和しうる半導体装置を提供することにある。
半導体装置の動作時において、鑞材部に生ずる熱応力は
、構成部材の熱膨張係数差、鑞材部、装置の湛度上昇等
で決まり、熱膨張係数差、及び幅度上昇は小さいほど望
ましい。−？方湛度上昇は装置の持つ熱抵抗と半導体チ
ップの発生損失とで決まり、やはり小さいほど望ましい
。従来熱応力緩和材としては半導体チップに熱膨張係数
の近いり／グステ／、モリブデン等を用いていたが、コ
スト、熱抵抗の点で問題があり、一方冷却フインとして
は、一般に銅、鉄、アルミニウム、リード材としては銅
が用いられていたが、銅、アルミニウムは放熱性は良い
が熱膨張係数の点で問題があり、鉄は熱膨張係数、コス
トの点では上記に比し良好であるが放熱性が劣るという
欠点があった。従って、本発明では放熱性、熱応力の問
題を同時に解決する材料として、複合材を用い、更に、
装置の放熱性を高めるため冷却フィン、リード側それぞ
れへの熱の拡がりが等価となるようにすることにより装
置の熱抵抗を等しくシ、かつ最小とすることに着目した
。
以下本発明の一実施例を第３図により説明する。
半導体チップ１、冷却フィン２、リード３が鑞材４ａ、
４ｂにより固着されており、冷却フィン２、リード３の
鑞材４ａ、４ｂと接着されている部分には複合材７が予
め固着されており冷却フィ／２の凹部にはシリコーンゴ
ム６が気密封止用絶縁物として充填されている。
複合材７の構造および、これを用いた冷却フィン２、リ
ード３の製法を説明する。
複合材の特徴は熱伝導性の良い銅マトリクス８に、熱膨
張係数の小さい炭素繊維９を第４図の如くうす巻き状、
もしくは第５図の如く網目状に配列し、通電加熱、もし
くは高周波加熱ホットプレスすることにより複合材７と
して完成される。次に第６図の如く銅、鉄またはアルミ
ニウム板１０の上に複合材７を重ね合わせて、再度ホッ
トプレスし、もしくは・第７図の如く鑞材１１を介して
接着させた後、プレス加工等により所定の冷却フィン２
やリード３の形状に加工すれば良い。
複合材７は半導体チップ１径方向への熱膨張係数が小さ
いので鑞材４ａ、４ｂの受けるせん断応力が小さく、ま
た熱伝導性に優れているので半導体チップ１において発
生した熱は速やかに放散される。この時半導体チップ１
からの発熱を冷却フイ／２、リード３側に等分に放散さ
せるため、熱の拡がり径を考慮して複合材７の径および
厚さが決められる。特に装置の熱抵抗を小さくするため
、リード３の半導体チップ１との接着面積（鑞付面）は
半導体チップ１の径と同等以上としている。
本発明において、装置に電流を断続的に通電して、臨度
サイクルを加える、いわゆる鑞材の熱疲労耐量試験を実
施した結果、従来装置では冷却フィン２側湛度上昇Ｔ、
とリード側湛度上昇Ｔ、との関係がＴ　Ｉ　＜　Ｔ　２
となっていたが、本発明装置ではＴ　ｔ　；Ｔ　ｔ　と
なったこと、また、半導体チップ１と冷却フィン２、半
導体チップ１とリード３との熱膨張係数差が小さくなっ
たことにより、熱疲労破壊寿命は大巾に向上出来たこと
が確認された。
【図面の簡単な説明】
第１図は従来装置の断面構造図、第２図は熱応力緩和材
を用いた従来装置の断面構造図、第３図は本発明による
装置の断面構造図、第４図（イ）、（ロ）はうずまき型
複合材の平面図および断面図、第５図（イ）、（ロ）は
網目型複合材の平面図および断面図、第６図は銅板に複
合材をホットプレスした断面図、第７図は銅板に複合材
を鑞材で接着した断面図である。 １・・・半導体チップ、２・・・冷却フィン、３・・・
リード、４ａ〜４Ｃ＋１１・・・鑞材、６・・・気密封
止用絶縁材、第４１２１　　　　　　　躬５図 （イ）　　　　　　　　　　　　　　　　　　　　　　
　　　　　　　　（イ２第に図　　　　第７図

Claims (1)

    【特許請求の範囲】
  1. １、半導体チップの両靜に冷却フィンとリードが鑞付さ
    れた半導体装置において、冷却フィンとリードの半導体
    チップ鑞付面に銅マトリクス中に炭素繊維を埋設してな
    る複合材を設け、半導体チップから冷却フィン、リード
    に至る熱抵抗をほぼ等しくする鑞付面を持つリードを用
    いたことを特徴とする半導体装置。
JP56130331A 1981-08-21 1981-08-21 半導体装置 Pending JPS5832423A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56130331A JPS5832423A (ja) 1981-08-21 1981-08-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56130331A JPS5832423A (ja) 1981-08-21 1981-08-21 半導体装置

Publications (1)

Publication Number Publication Date
JPS5832423A true JPS5832423A (ja) 1983-02-25

Family

ID=15031798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56130331A Pending JPS5832423A (ja) 1981-08-21 1981-08-21 半導体装置

Country Status (1)

Country Link
JP (1) JPS5832423A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719680A (en) * 1974-11-19 1982-02-01 Texas Instruments Inc Semiconductor chip and method of testing it
US5134463A (en) * 1989-10-23 1992-07-28 Mitsubishi Denki Kabushiki Kaisha Stress relief layer providing high thermal conduction for a semiconductor device
US5600809A (en) * 1993-06-30 1997-02-04 Mitsubishi Denki Kabushiki Kaisha Apparatus for sequentially reading microcode words wider than an external bus width to the outside in segments as wide as the external bus
JP2007214219A (ja) * 2006-02-08 2007-08-23 Hitachi Ltd 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5719680A (en) * 1974-11-19 1982-02-01 Texas Instruments Inc Semiconductor chip and method of testing it
JPH0122908B2 (ja) * 1974-11-19 1989-04-28 Texas Instruments Inc
US5134463A (en) * 1989-10-23 1992-07-28 Mitsubishi Denki Kabushiki Kaisha Stress relief layer providing high thermal conduction for a semiconductor device
US5600809A (en) * 1993-06-30 1997-02-04 Mitsubishi Denki Kabushiki Kaisha Apparatus for sequentially reading microcode words wider than an external bus width to the outside in segments as wide as the external bus
JP2007214219A (ja) * 2006-02-08 2007-08-23 Hitachi Ltd 半導体装置

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