JPS5830231A - Analog switching circuit with selector - Google Patents

Abstract

PURPOSE:To simplify a transistor array and wiring, and to improve integration density, by functionally using in common transistors constituting each independent functional circuit. CONSTITUTION:P channel FETs P1-P24 and N channel FETs N1-N24 constituting a transmission gate transistor for opening and closing an analog signal are combined in series and parallel by an optional number of pieces, and are connected. When to binary input data D1-D3, ''1'' is inputted, as for FFs F1-F3 for storing and outputting a selected data, Q1-Q3 become a high level. Accordingly, the N channel FET connected to the line of Q1-Q3 is turned on, and the P channel FET connected to the line of -Q1--Q3 is also turned on. In this case, a circuit whose transistors connected to 3 stages in series are all conducting becomes only a terminal (a), the terminal (a) is selected, and two-way transfer of an analog signal is executed between said terminal and an input/output common terminal X. After that, in accordance with a bindary input data, terminals (b)-(h) are selected.

Description

[Detailed description of the invention] The present invention uses an electronic circuit μ using an MO8 type FET.

Select n-series analog signals and extract any signal.
4L< relates to an analog switch circuit and a selector circuit for transmitting an arbitrary signal to a desired terminal in the n series.

Previously, J! ! ! An example of an electronic track configuration is bA1 when selecting and transmitting the output, or when selecting an arbitrary analog signal to the output terminals of several prefecture columns at an arbitrary timing and transmitting the output to the desired terminal. As shown in the figure, abcdefgh and I are input terminals for transmitting electrical analog signals, Ds, Da, and Ds are binary output selection signals, and OL is a gummy pulse.

Father, the breakdown of the circuit is the analog signal transmission of the n-series valve and the transnumination gate transistor (T1 to 71) for opening and closing.
The case of m h n =8 series will be explained below. ), and a decoder/selector circuit 5 consisting of an impark logic circuit for driving the transmission gate transistor (I to A) - a BAND logic circuit (Ns to Ns), and a flip for selection data generation and storage. It is a 70-tube circuit (Fs to IFs or hereinafter abbreviated as FF).

On the other hand, in the present invention, the transistors each having an independent functional circuit structure are functionally shared.

It aims to reduce the number of constituent transistors and simplify circuit wiring, and is an extremely effective and rational means for reducing chip size and cost by increasing integration density when used in integrated circuits. be.

Hereinafter, the detailed structure of the present invention will be explained with reference to the drawings.

FIG. 2 shows an example of the present invention, in which eight series are included in one drawing. In FIG.

Da, Ds are binary output selection signals; OL is a clock pulse h'lx, Fm, 'Fs is a selection data storage and output yy; j2. These signal names and functional circuits correspond to those in FIG. 1 (conventional configuration diagram), and indicate the same thing. Also bNm~N 14 ke N channel MOsgyET
f-PIP-Fs4 [P chaf $ MO day type FET is shown respectively.

Kao 1 figure 1 and 2, 5 and 4, 5 and 617 and 8, 9 and 10
．． 11 and 12.13 and 14.15 and 16°17 and 18.
19 and 20.21 and 22.23 and 24.25 and 26&2
Even if 7, 28, 29, 30, 131, and 32 are connected, the circuit operations described below are equivalent.

Here, the binarized selection signals Ds, Da,
Da is FF (Ft) from clock pulse (OL) K.

Fs, Fi) respectively, and output Qx-
, Qt@Qm1''Q*, Q-, Q, s are output.

If the desired terminal to be selected at this time is a, then D.

Da and Da are all H level (1), and when b is D1 digit 10W level (0), Da and Ds are each input data at H level (1).

The input data when the terminals c to h below are respectively desired to be selected are as shown in FIG.

If all children are selected, ti, FF output and QI
-'Hi level (decreases to I from now on) τ11111LOW
Level ll is expressed as 0) -Qt-work, τ3001Qs
-1, τs-0. Here, FETs (Ns~Ns*b Ps
-PSI) becomes conductive (ON) depending on the data signal level.
! ! However, when the data is output, I/1-) is, N, Nm, Ni.

Ns, Ny, N・ , Ni1l, Nil, N+a嘗N
1G.

Its, Pt, Pa, PI, PI, Pa,
Py.

The transistors P., 91g, P'l, Ps rings Pmv and Pus are turned on, and the other transistors are turned off. Here the transistors l 2 connected in 3 installation rows
5f N channel and P channel are all in ON state Conduction line ViNs 1 Ns, N of Ns
41I in the channel part and the P channel part of Ps, Pa, and Pa! The analog signal is transmitted between only the fc & terminal line and the input/output common terminal X where the a terminal is selected.

Father, if the data are D+ -0-Da-■, D■-1, then Nm, Ns, Na, Ns, Ni,
No.

8 layers, N1m, N14. N**, l'11t, N**
, P snow tP proverb, Pa, Pa, Pg
, Pe , Ps・, PSI, PI4゜P 1@
, P my , and F m- are each in the ON state, and Ni.

Nine analog switch sections consisting of Ha, Na, X'a, Ps, and Pa are turned on, and analog signals are transmitted between the b terminal and the common input/output terminal I.

Hereinafter, the same applies to the case of selecting the ch terminal (the data combinations are as shown in FIGS. 5 and 4).

The above explanation has been given using the case of 8 series selection as an example, but by changing the number of data bits and the III transistor arrangement, it is possible to easily configure an analog converter circuit with a bidirectional selector that can selectively switch any series. In addition, the present invention makes it possible to simplify the transistor arrangement and wiring. 5. When used in a tomb 9Q, etc., the present invention provides a great opportunity to improve the integration density.

[Brief explanation of the drawing]

Fig. 1 is a conventional circuit configuration diagram, and Fig. 2 is a vlI4 configuration diagram when Fig. 1 is replaced with Fig. 1 for the dormitory embodiment of the present invention. , the same signal and the same functional circuit? ffWasu. Figure 3 shows FFCF'1 for data output and storage. Fi, Fm) A pair of input data selection terminals for K (a~
h) shows the relationship. FIG. 4 is a chart showing the detailed relationship between the input data of the FF (Fs, Fi) and the FF output (Ql, x, Qm, τs, Qi, Tehatake). In addition, in FIG. 5 and FIG. 4, IFiH1 logic level, 0 represents LOW logic level. Applicant Shinshu Seiki Co., Ltd. Suwa Seikodai Agent Patent Attorney Tsutomu Mogami Figure 1 Figure 2

Claims (1)

[Claims] This is an electrical analog quantity transmission circuit using MO type field effect transistors (hereinafter abbreviated as FET), and has a transmission gate transistor that opens and closes n-series analog signals, and a selector that selects opening and closing of the transmission gate transistor. A circuit equipped with a circuit, P channel 1 that creates a 4ml transnussion gate transinutor for the Tsumugi F analog signal? By connecting any number of ICTs and N-channel PETs in series and in parallel, the FIT for forming the analog signal opening/closing transnuclear transistor i11 also serves as the 1PET for the selector circuit configuration. switch circuit.