JPS5826667B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5826667B2
JPS5826667B2 JP52025603A JP2560377A JPS5826667B2 JP S5826667 B2 JPS5826667 B2 JP S5826667B2 JP 52025603 A JP52025603 A JP 52025603A JP 2560377 A JP2560377 A JP 2560377A JP S5826667 B2 JPS5826667 B2 JP S5826667B2
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring
metal frame
film
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52025603A
Other languages
Japanese (ja)
Other versions
JPS53110370A (en
Inventor
博昭 藤本
正晴 野依
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP52025603A priority Critical patent/JPS5826667B2/en
Priority to US05/882,152 priority patent/US4246595A/en
Priority to GB8586/78A priority patent/GB1588377A/en
Priority to CA298,234A priority patent/CA1108305A/en
Priority to DE19782810054 priority patent/DE2810054A1/en
Publication of JPS53110370A publication Critical patent/JPS53110370A/en
Priority to US06/168,418 priority patent/US4356374A/en
Publication of JPS5826667B2 publication Critical patent/JPS5826667B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Description

【発明の詳細な説明】 本発明は半導体装置に関し、ワイヤレスボンデングがな
される半導体装置の取扱いを簡便とし、品質が均一でコ
ストの低減の可能なパッケージを提供するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and provides a package that simplifies the handling of a semiconductor device subjected to wireless bonding, has uniform quality, and can reduce costs.

さてミニモツド法は現在標準として125μ厚の樹脂フ
ィルムが使用されているが、この方法の問題の一つは、
フィルム材料として高価なポリイミドを使用しており薄
くするほど好ましいわけであるが、製作精度の点から薄
くすることが難しいことである。
Now, the MiniMotsudo method currently uses a resin film with a thickness of 125μ as the standard, but one of the problems with this method is that
Expensive polyimide is used as the film material, and the thinner it is, the better, but it is difficult to make it thinner from the viewpoint of manufacturing accuracy.

また、本出願人は配線密度を向上させるとともに、複数
の素子をフィルム上で相互配線するのに好適な方法を特
願昭50−92773号にて提案した。
In addition, the present applicant proposed in Japanese Patent Application No. 50-92773 a method suitable for improving wiring density and interconnecting a plurality of elements on a film.

この方法は、半導体素子の電極面と耐熱性絶縁樹脂フィ
ルムの一方の主面とが接着され、素子の電極上のフィル
ムに貫通孔を形成し、フィルムの他方の主面から金属配
線を形成すると同時に電極と金属配線を貫通孔を利用し
て相互接続するものである。
In this method, the electrode surface of a semiconductor element and one main surface of a heat-resistant insulating resin film are adhered, a through hole is formed in the film on the electrode of the element, and a metal wiring is formed from the other main surface of the film. At the same time, the electrodes and metal wiring are interconnected using through holes.

この方法は貫通孔を形成する必要からフィルム自体は5
0〜20μ程度に必然的に薄いものとなり、配線の形成
の精度、自由度が高まるとともにコストの面でも極めて
有利となる。
This method requires the formation of through holes, so the film itself has a diameter of 5.
It is necessarily thin, on the order of 0 to 20 μm, which increases the precision and freedom of wiring formation and is extremely advantageous in terms of cost.

しかるに、ミニモツド法ならびに本出願人の提案した方
法においてもフィルムを薄くしたときに起る共通的な問
題は、薄いフィルムの取扱いの困難性であり、そのため
電気的特性の測定時あるいはプリント基板への実装時に
問題を生ずることである。
However, a common problem that arises when thinning films in both the Minimod method and the method proposed by the applicant is the difficulty in handling thin films, which makes it difficult to handle them when measuring electrical characteristics or attaching them to printed circuit boards. This causes problems during implementation.

本発明はこのような問題に鑑み、樹脂フィルムを薄くし
ても充分その強度が保てるような半導体装置を得るもの
である。
In view of these problems, the present invention provides a semiconductor device that can maintain sufficient strength even if the resin film is made thin.

以下本発明の一実施例にかかる半導体装置を図面ととも
に説明する。
A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

この実施例は前述の本出願人提案の構造に本発明を適用
したものである。
This embodiment is an application of the present invention to the structure proposed by the applicant mentioned above.

1は半導体素子で一生面に電極端子(図示せず)が形成
されており、この−主面が薄い熱可塑性樹脂(FEP)
2を介してたとえばポリイミドよりなる耐熱性樹脂フィ
ルム基板3の一方の面に接着されている。
1 is a semiconductor element with electrode terminals (not shown) formed on its entire surface, and this main surface is made of thin thermoplastic resin (FEP).
2 to one side of a heat-resistant resin film substrate 3 made of polyimide, for example.

そして、電極端子の対応する位置の基板3の一部に貫通
孔4が形成されており、基板3の他方の面にはたとえば
蒸着金属配線5が形成され、貫通孔4の部分にて金属配
線5と電極端子とが接続される構成となっている。
A through hole 4 is formed in a part of the substrate 3 at a position corresponding to the electrode terminal, and a vapor-deposited metal wiring 5, for example, is formed on the other surface of the substrate 3, and the metal wiring is formed in the through hole 4. 5 and an electrode terminal are connected to each other.

6は本発明の特徴とするフィルム基板2補強用の金属枠
体よりなる支持体で、第2図に示されているように素子
1より薄く形成されている。
Reference numeral 6 denotes a support made of a metal frame for reinforcing the film substrate 2, which is a feature of the present invention, and is formed thinner than the element 1, as shown in FIG.

この金属枠体6は、素子1の周囲の一方の面にFEPを
介して接着されている。
This metal frame 6 is bonded to one side of the periphery of the element 1 via FEP.

7は保護用の樹脂で金属枠体6と素子1問および素子1
の表面上に形成されている。
7 is a protective resin with metal frame 6, element 1 and element 1.
is formed on the surface of

さて、第1,2図の構造の半導体装置はまず、テーパー
状の貫通孔4の形成された50〜20μ程度のポリイミ
ドフィルム1上に上記金属枠体6を、10μ〜2μ程度
のFEP2を介して接着し、そして、半導体素子1を約
3000Cの温度で圧着により接着固定する。
Now, in the semiconductor device having the structure shown in FIGS. 1 and 2, first, the metal frame 6 is placed on a polyimide film 1 with a thickness of about 50 to 20 μm in which a tapered through hole 4 is formed, and an FEP 2 with a thickness of about 10 μ to 2 μm is interposed therebetween. Then, the semiconductor element 1 is bonded and fixed by pressure bonding at a temperature of about 3000C.

そして、Cu、Al、Niなどの金属を蒸着、メッキな
どの手段により形成し、金属配線5の所定パターンを形
成する。
Then, a metal such as Cu, Al, Ni, etc. is formed by means such as vapor deposition or plating to form a predetermined pattern of the metal wiring 5.

この配線5の厚みは半導体素子1の電流容量にもよるが
一般的には2〜20μ程度である。
The thickness of this wiring 5 depends on the current capacity of the semiconductor element 1, but is generally about 2 to 20 microns.

そして必要に応じて、樹脂7.プリント基板等への接続
のために配線5の表面の1部にAu、Sn+半田メッキ
(図示せず)を施こすことにより第1,2図の装置を作
成することができる。
And if necessary, resin 7. The devices shown in FIGS. 1 and 2 can be produced by applying Au, Sn+ solder plating (not shown) to a part of the surface of the wiring 5 for connection to a printed circuit board or the like.

金属枠体6は第1図に示す様に少くともフィルム基板3
の周辺全領域に亘る様にする。
The metal frame 6 is attached to at least the film substrate 3 as shown in FIG.
Cover the entire area around the area.

これはフィルム基板3がそらない様にするためと強度に
対する考慮のためである。
This is to prevent the film substrate 3 from warping and to consider the strength.

比較的フィルム面積が大きい場合にはそれだけでは不十
分な場合があるので第1図に示す様な半導体素子の周辺
にも及ぶ様な枠体を用いてもよい。
If the film area is relatively large, this alone may not be sufficient, so a frame body that extends around the semiconductor element as shown in FIG. 1 may be used.

この様に半導体素子を取囲こむ様に金属枠体6を形成し
た場合にはそれとは別に次の効果を生ずる。
When the metal frame 6 is formed so as to surround the semiconductor element in this way, the following effect is produced separately from this.

すなわち半導体素子の表面にフィルム基板3に接着して
いるため外部に対する保護は一応されている構造になっ
ているが環境によっては更に裏面より樹脂7で封止した
い場合にこの枠体6が樹脂の余分な領域へのはみだしに
対するストッパーの役割を果す。
In other words, since the surface of the semiconductor element is bonded to the film substrate 3, it has a structure that protects it from the outside, but depending on the environment, if it is desired to further seal it with resin 7 from the back side, this frame 6 may be covered with resin. It acts as a stopper to prevent it from protruding into unnecessary areas.

金属枠体6の厚さは30μから500μ程度であり材質
としてはCu、ステンレス、Fe等である。
The thickness of the metal frame 6 is about 30μ to 500μ, and the material is Cu, stainless steel, Fe, etc.

この材質の選択に際しては配線材料などによっても異る
The selection of this material also depends on the wiring material, etc.

すなわち配線材料が例えばCuの場合、フォトリソ技術
及びエツチングで配線パターンを形成する場合にはCu
のエツチング液例えばFeCl3溶液に耐える様な金属
材質例えばステンレスを用いる事が必要となる。
In other words, when the wiring material is Cu, for example, Cu is used when forming the wiring pattern by photolithography and etching.
It is necessary to use a metal material such as stainless steel that can withstand the etching solution such as FeCl3 solution.

また半導体素子部のみを除いた巾の大きい金属体形状の
ものを用いずに、第1図に明らかなとおり細いフレーム
よりなる金属枠体を用いると、巾の太きいものでは接着
の際にフィルム基板3と金属枠体間に気泡が入り易く均
一に接着することが難かしいが、第1図の形状では容易
に均一に接着させる事が可能である。
Also, if you use a metal frame made of a thin frame as shown in Figure 1, instead of using a metal frame with a large width that excludes only the semiconductor element part, it is possible to use a thin metal frame as shown in Figure 1. Air bubbles tend to enter between the substrate 3 and the metal frame, making it difficult to bond them uniformly, but with the shape shown in FIG. 1, it is possible to bond them easily and uniformly.

さらにこの形状のもう一つの利点はプリント基板等に本
装置を接着あるいは接続する際に不必要に熱容量を大き
くしないでよいために例えば半田付けで接続する際など
に短時間に接続可能となる。
Furthermore, another advantage of this shape is that when bonding or connecting the present device to a printed circuit board or the like, it is not necessary to increase the heat capacity unnecessarily, so that connection can be made in a short time, for example, when connecting by soldering.

また、第3図は、第1,2図の構造においてフィルム基
板3上に複数個の半導体素子1がある場合に本発明を適
用したものを示したものであり、この場合も第1,2図
と同様の効果を発揮することができる。
Moreover, FIG. 3 shows the structure in which the present invention is applied when there are a plurality of semiconductor elements 1 on the film substrate 3 in the structure shown in FIGS. The same effect as shown in the figure can be achieved.

以上の説明は、本出願人の提案した構造に本発明を適用
した例を述べたが、本発明は通常のミニモツド方式のよ
うに半導体素子とフィルム基板上の配線が銅のビームに
より接続されている様な構造の時にも同様に金属枠体6
を設けることにより同様の効果を得ることができる。
The above explanation describes an example in which the present invention is applied to the structure proposed by the applicant, but the present invention is similar to the normal minimod system in which the semiconductor element and the wiring on the film substrate are connected by copper beams. Similarly, when the structure is such that the metal frame 6
A similar effect can be obtained by providing .

以上のように、本発明は取扱いが困難な薄い樹脂フィル
ム基板と半導体素子よりうすい金属枠体よりなる支持体
とを一体化することにより、フィルム基板をより薄くす
ることを可能とするとともに、その取扱いを容易とし、
特に電気的測定を行う際あるいはプリント板等に取付け
る際に能率が向上しトータルコス+の低減が可能となり
、ワイヤレスボンディングを用いる半導体装置の作成に
大きく寄与するものである。
As described above, the present invention makes it possible to make the film substrate thinner by integrating a thin resin film substrate that is difficult to handle with a support made of a metal frame thinner than a semiconductor element, and also makes it possible to make the film substrate thinner. Easy to handle,
In particular, efficiency is improved and total cost can be reduced when performing electrical measurements or when attaching to a printed board, etc., and this greatly contributes to the production of semiconductor devices using wireless bonding.

さらに本発明は樹脂コーティングを施した際、樹脂のは
みだしが起らず、品質的に均一なものを得ることができ
、工業的にすぐれた効果を奏する。
Furthermore, when the present invention is applied with a resin coating, the resin does not ooze out, and a uniform product can be obtained in terms of quality, resulting in excellent industrial effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例にかかる半導体装置の平面図
、第2図は第1図のn −n’線断面図、第3図は複数
個の半導体素子を用いた場合の本発明の他の実施例にか
かる平面図である。 1・・・・・・半導体素子、2・・・・・・熱可塑性樹
脂、3・・・・・・耐熱性樹脂フィルム基板、4・・・
・・・貫通孔、5・・・・・・金属配線、6・・・・・
・金属枠体、7・・・・・・樹脂。
FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line n-n' in FIG. FIG. 3 is a plan view of another embodiment of the present invention. 1... Semiconductor element, 2... Thermoplastic resin, 3... Heat resistant resin film substrate, 4...
...Through hole, 5...Metal wiring, 6...
・Metal frame, 7...Resin.

Claims (1)

【特許請求の範囲】[Claims] 1 絶縁樹脂フィルム基板の一生面上に選択的に外部引
出し用配線が形成され、上記半導体素子が絶縁性樹脂フ
ィルムの他主面上に接着され、上記半導体素子上の上記
絶縁性樹脂フィルムの一部に貫通孔が形成され、半導体
素子の電極端子と外部引出し用配線が上記貫通孔を介し
て接続され、上記素子の周辺部の一部において上記フィ
ルムの他主面上にその厚みが前記素子の厚みより薄い金
属枠体よりなる支持体を形成してなることを特徴とする
半導体装置。
1 External lead wiring is selectively formed on one surface of the insulating resin film substrate, the semiconductor element is adhered to the other main surface of the insulating resin film, and one of the insulating resin films on the semiconductor element is bonded to the other main surface of the insulating resin film. A through hole is formed in the part, and the electrode terminal of the semiconductor element and the wiring for external extraction are connected through the through hole, and the thickness of the semiconductor element is formed on the other main surface of the film in a part of the peripheral part of the element. 1. A semiconductor device comprising a support made of a metal frame thinner than the thickness of the semiconductor device.
JP52025603A 1977-03-08 1977-03-08 semiconductor equipment Expired JPS5826667B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP52025603A JPS5826667B2 (en) 1977-03-08 1977-03-08 semiconductor equipment
US05/882,152 US4246595A (en) 1977-03-08 1978-02-28 Electronics circuit device and method of making the same
GB8586/78A GB1588377A (en) 1977-03-08 1978-03-03 Electronic circuit devices and methods of making the same
CA298,234A CA1108305A (en) 1977-03-08 1978-03-06 Electronic circuit device and method of making the same
DE19782810054 DE2810054A1 (en) 1977-03-08 1978-03-08 ELECTRONIC CIRCUIT DEVICE AND METHOD OF MANUFACTURING IT
US06/168,418 US4356374A (en) 1977-03-08 1980-07-10 Electronics circuit device and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52025603A JPS5826667B2 (en) 1977-03-08 1977-03-08 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS53110370A JPS53110370A (en) 1978-09-27
JPS5826667B2 true JPS5826667B2 (en) 1983-06-04

Family

ID=12170474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52025603A Expired JPS5826667B2 (en) 1977-03-08 1977-03-08 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5826667B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57145354A (en) * 1980-11-21 1982-09-08 Gao Ges Automation Org Carrier element for ic module
JP4563166B2 (en) 2004-12-17 2010-10-13 日本テトラパック株式会社 Filling machine and filling monitoring method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519587A (en) * 1974-07-12 1976-01-26 Sharp Kk Handotaisochino seizoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS519587A (en) * 1974-07-12 1976-01-26 Sharp Kk Handotaisochino seizoho

Also Published As

Publication number Publication date
JPS53110370A (en) 1978-09-27

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