JPS58219807A - Amplifier for pulse width modulation - Google Patents

Abstract

PURPOSE:To attain feedback precisely with a simple circuit configuration by subtracting the outputs of two pulse amplifiers having BTL constitution each other and feeding back the subtracted value to an integrated circuit of an input stage. CONSTITUTION:The outputs of the pulse amplifiers 3, 4 which drive a load 16 by their output signals having reverse phase each other are subtracted each other by a subtracting circuit 6 and the subtracted result ef is fed back to the integrated circuit 1 of the input stage and, simultaneously, a signal ei to be amplified is inputted. The output ex of the integrated circuit 1 is compared with a carrier signal ec by a comparator 2 and the output ep of the comparator 2 drives the pulse amplifiers 3, 4. Consequently, the balanced output of a BTL output stage constituted by the pulse amplifiers 3, 4 can be fed back stably to the integrated circuit constituting the input stage, reducing distortion sharply.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse width modulation amplifier having an output stage pulse amplification circuit having a BT]u configuration, and particularly to a pulse width modulation FA amplification gain in which feedback is applied in a novel manner.

The pulse width variable V4 amplifier converts an input signal such as an audio signal into a pulse (H
Then, efficient amplification is performed in the form of a pulse signal, and then t11! - to obtain the output. In such a pulse width modulation amplifier, usually
It is essential to provide negative feedback to reduce distortion.

By the way, in order to improve the power usage efficiency in this conventional pulse width modulation amplifier, it is desirable to use a pulse amplification circuit or TL structure in the output stage. Shikajina ρ Tamera B
If the TL1fN configuration is used, the output will be balanced (symmetrical with respect to the ground plane), so it will be impossible to apply feedback as is to a normal unbalanced input stage. In this case, it is conceivable to provide an input stage individually for each pulse amplification circuit in the BTL output stage and apply negative feedback between each output stage and input stage. Compared to the case where feedback is applied, the number of circuit parts is twice as many, which is extremely uneconomical.

In view of the above circumstances, the present invention provides a pulse width modulation amplifier that can provide reliable feedback with an extremely simple circuit configuration when the output stage has a BTL configuration. The first . and a second pulse amplification circuit, wherein the first. A subtraction circuit is provided to take one output signal of the second pulse jillIfi & circuit and the output signal of the other, and the output signal of this subtraction circuit is fed back to the integration circuit.

Hereinafter, ρS will be explained in detail with reference to the drawings, which are examples of the present invention.

FIG. 1 is a circuit diagram showing a first embodiment of a pulse width modulation amplifier according to the present invention. Pulse width variation V shown in this figure
The @amplifier is of a type in which a carrier signal is input within the feedback loop.

First, to describe the schematic structure of the pulse width modulation amplifier shown in FIG. It shows a comparator that compares . Also, code 3 is #gl which amplifies the output of comparator 2 in the same phase.
The reference numeral 4 designates a second pulse amplification circuit that amplifies the output of the comparator 2 in No. 61 with the opposite phase. And these first. Second pulse amplification circuit 3,4 BT
The L-connection is used to drive both ends of the speaker 5 (load) with signals having opposite phases. Further, reference numeral 6 denotes the output of the pulse amplifying circuit 4 (from the output signal N to the pulse amplifying circuit 3).
This subtraction circuit 6 subtracts the output signal of
The output signal of is fed back to the integrating circuit l.

The configuration of this pulse width modulation amplifier will be described in detail below.The integrating circuit 1 includes an operational amplifier 7, a capacitor 8 (value C) inserted between the output terminal and the inverting input terminal of the operational amplifier 7. , one end of the resistor 9 (
1 straight R), an input terminal 10a and a ground terminal 1
0b (signal to be amplified) is input to the non-inverting input terminal of the operational amplifier 7. The output terminal of this S amplifier 7 is connected to the Q input terminal of the comparator 2. The Φλ input terminal of the comparator 2 is supplied with a triangular wave carrier 4M generated by the carrier signal source 11. In this case, the frequency of the carrier signal e6 is a constant value that is sufficiently higher than the upper limit frequency of the signal e1. The output of this comparator 2 is a power type field effect transistor (hereinafter abbreviated as power FF1tT) 4a that constitutes an inverted pulse width circuit 4.
, 4b, and the inverting amplifier 12 constituting the non-inverting pulse amplification circuit 3 and the power Fil! It is supplied to both gates of T3a and T3b.

-Power FFl! 73m, 4g both sources and power ti
A power supply voltage E is supplied from a power supply 13 between the sources of T3, b, and 4b. In this case, a resistor 14H2t4b (1
Both resistors 14a and 14b are connected in series, and the connection point between these two resistors 14a and 14b is grounded via the voltage follower circuit 15, thereby increasing the power of the power source. I
The voltage applied to both sources of IIT3a and 4m and the power pI! ! The voltages applied to both sources of T3b and 4b m are maintained at +2 and -i, respectively. On the other hand, the power FITs 3a and 3b
Both drains of the speaker 5 are connected in common, and are connected to the speaker 5 through the single-power winding 168 of the transformer 16 and the terminal 17m in sequence.
The power transistors 4a and 4b are connected to one end of the power transistors 4a and 4b.
Both drains of the speaker 5 are connected in common, and are connected to the speaker 5 via the other winding 16b of the transformer 16 and the terminal 17b in sequence.
connected to the other end. And terminal 17g and terminal 17
A capacitor 18 is inserted between the In this case, the transformer 16 and the capacitor 18 constitute a filter circuit that blocks the carrier signal component in the output of the pulse amplification circuit 3.4. On the other hand, the power FBT3a,
The common drain of power FFIT 4m and 4b is connected to the inverting input terminal of the N amplifier 200 through the resistor ``a (IUR+)'', and the common drain of power FFIT 4m and 4b is connected to the resistor 191) (
R', ) is connected to the non-inverting input terminal of the operational amplifier 20. A resistor 21b (value R't) is connected between the non-inverting input terminal of the operational term #A unit 20 and the ground point.
A resistor 21 a (It[Rt) is inserted between the inverting input terminal and the output terminal of the S amplifier 20, and the output terminal of the S amplifier 20 is connected to the resistor 9. connected to the other end. In this case, the power Fl! From the common drain voltage of 1T4a, 4b, the power FF1iT3a, 3b
A subtraction circuit 6 is configured to subtract the common drain voltage of .

Next, the operation of this embodiment with the above configuration will be explained with reference to the time chart of FIG.

First, assume that at time (o) shown in FIG. 2(a), the relationship between the carrier signal e6 shown by the solid line and the output signal ex of the operational amplifier 7 shown by the dashed line is ex)ea. In this case, the output signal Np of the comparator 2 is as shown in FIG.
As shown in b), the signal eO at the common drain of the power FFITs 3a and 3b was at V@voltage-7 as shown in b) of the same figure, and the power FF! T
The signal voltage at the common drain of 4a and 4b is approximately at a voltage as shown in the same figure). -It has become Town X. On the other hand, the voltage at the inverting input terminal of the operational amplifier 7 is always equal to the voltage of the signal f51' due to the nature of the operational amplifier provided with feedback. Therefore, at the time i0, a current flows toward the output terminal of the operational amplifier 7 through the resistor 9 and the capacitor 8 in order, and the voltage of the signal -@eI decreases.

Then, at time t shown in FIG. 2(a), the carrier signal Pa and the signal F! Suppose that the relationship with violet changes from ex)ea to eg×ea, the signal eν shifts from low level to high level, and as a result, the signal ef changes from voltage E to voltage −SER,R.

As a result, a current C starts to flow from the output terminal of the operational amplifier 7 through the capacitor 8 and the resistor 9 in sequence. As a result, the voltage of the signal PX increases according to the current of equation (2), as shown in period T in FIG. 2(a).

Next, when the period T elapses and the relationship between the voltage of the signal Qx and the voltage of the carrier signal ee is reversed, the signal p p changes from high level to low level. The current shown in equation (1) above is made to flow toward the output terminal of the operational amplifier 7 through the serial terminals, so that the voltage of the signal line becomes as shown in period TI in FIG. 2 (a). The current decreases according to equation (1).

Then, after this period T has passed, the relationship between the voltage of the carrier signal PM and the voltage of the carrier signal pa becomes old and reverses, and the above-described operation is repeated in the same manner.

ζNow, when considering the relationship between the periods T and the period T, that is, the duty ratio, the amount of voltage rise of the signal ex in the period TI is equal to the voltage drop of the same signal in the period T, so the following holds true. . Then, the duty ratio becomes, and it can be seen that it is proportional to the signal e1 to be amplified.

In this way, the integration circuit 1 → comparator 2 → pulse amplification circuit 3
, 4→subtraction circuit 6→integration circuit l has the same frequency as the carrier signal ea and the signal e1
A pulse signal eo with a duty ratio proportional to the amplitude of
, it is possible to obtain eo.

On the other hand, the pulse signal eO obtained in this manner.

After the signal component of the carrier signal eu is removed and demodulated by a filter circuit including a transformer 16 and a capacitor 18, dCI is supplied to both ends of the speaker 50 as output signals having opposite phases. In this case, the currents of these output signals of both positive and negative phases are balanced by the transformer 16.

According to the embodiment shown in FIG. 1, the balanced output (
The signals eo, eo) can be negatively fed back extremely stably to the integrating circuit 1 constituting the input stage, thereby making it possible to significantly reduce distortion. Note that the gain of the pulse width modulation amplifier according to this embodiment is determined by the resistance value R8 and the resistance value R8.
It can be determined by the ratio with 9.

Next, the configuration of a second embodiment of the present invention is shown in FIG.

The pulse width modulation amplifier shown in FIG. 3 is of a type in which a carrier signal is input from outside the feedback loop, and in this diagram, parts corresponding to those in FIG. 1 are given the same reference numerals. The explanation will be omitted. In FIG. 3, the configuration of this pulse width modulation amplifier is the same as that of the pulse-variable I term width amplifier shown in FIG. ea7
) is supplied to the inverting input terminal of the differential amplifier 70 via the S resistor 23, the output terminal of the differential amplifier 7 is connected to the input terminal of the comparator 2, and the eThe input terminal is at the point where it is grounded.

The pulse amplifying circuit 3 is a non-inverting pulse amplifying circuit, and the pulse amplifying circuit 4 is an inverting pulse amplifying circuit.

Next, the operation of this embodiment with the above configuration will be explained. First, the integrating circuit 1 integrates the rectangular wave carrier signal pa using the resistor 23 and the capacitor 8 to generate a triangular wave, adds the voltage of the signal ei to the triangular wave, and outputs the result. The signal ex becomes a triangular wave that changes according to the DC level furnace signal 611C, for example, as shown in FIG. 4(A).

This signal ex is then compared to ground level. Therefore, as shown in FIG. 4(b), the signal eν is a pulse signal having the same frequency as the Φ signal eo and whose duty ratio is proportional to the amplitude of the signal e1. This signal e) is amplified by pulse amplification circuits 3 and 4, respectively, to produce signals eo,;;

Then, the transformer 16 and the capacitor 18 are sequentially operated and the signal is supplied to the speaker 5. On the other hand, the subtraction circuit 6
pa is subtracted from , and the result of this subtraction (signal et) is fed back to the integrating circuit 1 via the resistor 9.

Therefore, in the embodiment shown in FIG. 3, the balanced output (signal 6ojo) of the BTL output stage composed of pulse amplification circuits 3 and 4 is extremely stably transmitted to the integrating circuit l constituting the input stage. It is possible to provide negative feedback to the sensor, which can significantly reduce distortion.

As is clear from the above description, the pulse width converter according to the present invention includes an integrating circuit that inputs a signal to be amplified, a comparator that uses the output of this integrating circuit as one comparison input, and a BTL connected first . a second pulse amplification circuit;
A subtraction circuit for subtracting one output signal of the second pulse amplification circuit from the other output signal is provided, and the output of the subtraction circuit is fed back to the integrator circuit. When using a pulse amplifier circuit with a BTL configuration to increase power usage efficiency, stable negative feedback can be applied with an extremely simple circuit configuration, thereby increasing power usage efficiency.
It is possible to realize a pulse width modulation amplifier that is inexpensive and has a low distortion factor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a pulse width modulation amplifier according to the present invention, FIG. 2 is a time chart for explaining the operation of the same embodiment, and FIG.
FIG. 4 is a circuit diagram showing the configuration of the embodiment, and FIG. 4 is a time chart for explaining the operation of the embodiment. l...Integrator circuit, 2...Comparator, 3...First pulse amplification circuit, 4...Second pulse amplification circuit, 5...
-Load (speaker'), 6...subtraction circuit. Applicant: Nippon Musical Instruments Manufacturing Co., Ltd.

Claims (1)

[Claims] The first type drives both ends of the load with output signals having opposite phases to each other.
a second pulse amplification circuit, a subtraction circuit that subtracts the output signal of one of these first and second pulse amplification circuits from the other output signal, and a subtraction circuit that subtracts the output signal of the subtraction circuit and the signal to be amplified. an integrator circuit which takes as inputs, and an output signal of this integrator circuit which is used as one comparison input, and the comparison output is used as the first
．． A pulse width modulation amplifier characterized by comprising a comparator that drives a second pulse amplification circuit.