JPS58216449A - Semiconductor device and substrate used for assembling therefor - Google Patents

Semiconductor device and substrate used for assembling therefor

Info

Publication number
JPS58216449A
JPS58216449A JP57097821A JP9782182A JPS58216449A JP S58216449 A JPS58216449 A JP S58216449A JP 57097821 A JP57097821 A JP 57097821A JP 9782182 A JP9782182 A JP 9782182A JP S58216449 A JPS58216449 A JP S58216449A
Authority
JP
Japan
Prior art keywords
resin
semiconductor
region
flow
undercoating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57097821A
Other languages
Japanese (ja)
Inventor
Kenji Akeyama
Yoshimi Hagiwara
Nobukatsu Tanaka
Norio Yoshihara
Original Assignee
Hitachi Ltd
Hitachi Tobu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tobu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP57097821A priority Critical patent/JPS58216449A/en
Publication of JPS58216449A publication Critical patent/JPS58216449A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PURPOSE:To reduce the number of manufacturing steps and the cost of a product by hardly flowing out undercoating resin from an undercoated region which is formed with a groove extending in an endless shape. CONSTITUTION:After a semiconductor element 14 is secured onto the semiconductor element mounting region 2 of a header 5, the prescribed electrodes of the element 14 are connected via wirings 15 to the inner ends of the leads 8 at both sides, and the element 14 is covered with undercoating resin 16. Since a sharp corner which is produced due to the flowout of resin is not present at the peripheral edge of an undercoated region 4 in this case, the resin does not flow out. After the resin 16 is then hardened, a resin molding region 17 is molded with epoxy resin, and the prescribed part is covered with a resin package 18. Thereafter, unnecessary frame 11 and dam 12 are cut and removed, and a semiconductor device 19 is manufactured. Since the undercoating resin does not override to flow out in the assembly in this manner, the sampling work for flow- out resin can be eliminated.
JP57097821A 1982-06-09 1982-06-09 Semiconductor device and substrate used for assembling therefor Pending JPS58216449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57097821A JPS58216449A (en) 1982-06-09 1982-06-09 Semiconductor device and substrate used for assembling therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57097821A JPS58216449A (en) 1982-06-09 1982-06-09 Semiconductor device and substrate used for assembling therefor

Publications (1)

Publication Number Publication Date
JPS58216449A true JPS58216449A (en) 1983-12-16

Family

ID=14202397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57097821A Pending JPS58216449A (en) 1982-06-09 1982-06-09 Semiconductor device and substrate used for assembling therefor

Country Status (1)

Country Link
JP (1) JPS58216449A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008121726A1 (en) * 2007-03-30 2008-10-09 Finisar Corporation Non-uniform feedthrough and lead configuration for a transistor outline package
US7950839B2 (en) 2007-04-02 2011-05-31 Chimei Innolux Corporation Light emitting diode having electrodes with branches and backlight module using same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008121726A1 (en) * 2007-03-30 2008-10-09 Finisar Corporation Non-uniform feedthrough and lead configuration for a transistor outline package
US8093710B2 (en) 2007-03-30 2012-01-10 Finisar Corporation Non-uniform feedthrough and lead configuration for a transistor outline package
US7950839B2 (en) 2007-04-02 2011-05-31 Chimei Innolux Corporation Light emitting diode having electrodes with branches and backlight module using same

Similar Documents

Publication Publication Date Title
EP0833382B1 (en) Plastic package for electronic devices
KR910002292B1 (en) Semiconductor device and manufacturing method thereof
US4663833A (en) Method for manufacturing IC plastic package with window
JP3504297B2 (en) Semiconductor device having a die supporting member having an opening
US6194251B1 (en) Die positioning in integrated circuit packaging
EP0813236B1 (en) Method for encapsulating an integrated semi-conductor circuit
US5926380A (en) Lead frame lattice and integrated package fabrication method applied thereto
KR960009136A (en) Semiconductor package and manufacturing method
KR950001854A (en) A manufacturing method of a resin encapsulated semiconductor device, a lead frame for installing a plurality of semiconductor elements used in the manufacturing method, and a resin encapsulated semiconductor device manufactured by this manufacturing method
WO2004093128A3 (en) Lead frame structure with aperture or groove for flip chip in a leaded molded package
JPH0722560A (en) Lead frame for semiconductor device
US5115299A (en) Hermetically sealed chip carrier with ultra violet transparent cover
JPS59227143A (en) Package of integrated circuit
JPS63205935A (en) Resin-sealed type semiconductor device equipped with heat sink
JPS60195957A (en) Lead frame
KR920007133A (en) Integrated circuit device and method for preventing cracking during surface mounting
KR970067736A (en) Lead frame, semiconductor device using same and manufacturing method thereof
JPH09129785A (en) Semiconductor element with a package body where the outline of a die was formed and its preparation
JPH0225057A (en) Manufacture of semiconductor device
KR940001363A (en) Low Profile Overmolded Pad Array Semiconductor Device and Manufacturing Method Thereof
KR960019690A (en) Manufacturing Method of Semiconductor Device
JPH01155635A (en) Carrier tape
JPS58207657A (en) Manufacture of semiconductor device
KR960026692A (en) Semiconductor package and manufacturing method
JPS57147260A (en) Manufacture of resin-sealed semiconductor device and lead frame used therefor