JPS58214947A - Information processor - Google Patents

Information processor

Info

Publication number
JPS58214947A
JPS58214947A JP9987882A JP9987882A JPS58214947A JP S58214947 A JPS58214947 A JP S58214947A JP 9987882 A JP9987882 A JP 9987882A JP 9987882 A JP9987882 A JP 9987882A JP S58214947 A JPS58214947 A JP S58214947A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
address
contents
set
register
action
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9987882A
Inventor
Toshiteru Shibuya
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355Indexed addressing, i.e. using more than one address operand

Abstract

PURPOSE:To realize indirect access action of the highest speed, by discriminating the type of a data describer, and then using either one of effective action between addition action and effective access action of a memory system. CONSTITUTION:When a control circuit 50 starts its operation, the contents are read out for a base register 11 which is designated by the address syllable of an instruction held at an instruction register 10. At the same time, the contents of a general-purpose register 12 designated said address syllable are selected by a selector 20 since the selection signal is set at 0. In the same way, the displacement of the address syllable is selected by a selector 21 and with a selection signal. After a 1T cycle from the start of operation of the circuit 50, the contents of designated registers 11 and 12 are set to address registers 22 and 23 respectively. At the same time, the displacement of the address syllable is set to an address register 24. These contents and displacement are added together by an address adder 30, and the result of addition is selected by a selector 25 since the selection signal is set to 0.
JP9987882A 1982-06-09 1982-06-09 Information processor Pending JPS58214947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9987882A JPS58214947A (en) 1982-06-09 1982-06-09 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9987882A JPS58214947A (en) 1982-06-09 1982-06-09 Information processor

Publications (1)

Publication Number Publication Date
JPS58214947A true true JPS58214947A (en) 1983-12-14

Family

ID=14259058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9987882A Pending JPS58214947A (en) 1982-06-09 1982-06-09 Information processor

Country Status (1)

Country Link
JP (1) JPS58214947A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2637098A1 (en) * 1988-09-26 1990-03-30 Nec Corp Logic address generator device for an instruction specifying two words, each divided into two parts
JPH02236727A (en) * 1989-03-10 1990-09-19 Koufu Nippon Denki Kk Information processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2637098A1 (en) * 1988-09-26 1990-03-30 Nec Corp Logic address generator device for an instruction specifying two words, each divided into two parts
JPH02236727A (en) * 1989-03-10 1990-09-19 Koufu Nippon Denki Kk Information processor

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