JPS5820032A - Resetting circuit - Google Patents

Resetting circuit

Info

Publication number
JPS5820032A
JPS5820032A JP11802981A JP11802981A JPS5820032A JP S5820032 A JPS5820032 A JP S5820032A JP 11802981 A JP11802981 A JP 11802981A JP 11802981 A JP11802981 A JP 11802981A JP S5820032 A JPS5820032 A JP S5820032A
Authority
JP
Japan
Prior art keywords
voltage
circuit
power supply
vth
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11802981A
Other languages
Japanese (ja)
Inventor
Naoyoshi Uesugi
通可 植杉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11802981A priority Critical patent/JPS5820032A/en
Publication of JPS5820032A publication Critical patent/JPS5820032A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Abstract

PURPOSE:To ensure correct resetting during turning-on and -off of a power supply and during a drop of voltage, by extracting the voltage to be compared with the voltage which is proportional to the power supply voltage out of the power supply voltage via a constant voltage element. CONSTITUTION:A voltage divider consists of resistances R1 and R2. A Zener diode 4 is connected between a voltage applying point A and the resistance R1, and a capacitor C3 is connected in parallel with the resistance R2. The power supply voltage VA and the both-end voltage VB of the C3 are led to a deciding circuit 5. The circuit 5 compares the voltage VB with voltage VTH(=1/2VA) which is proportional to the voltage VA and delivers a reset signal VO when VB<VTH is obtained. When the power supply is applied, the voltage VTH increases as the rise of the voltage VA. The voltage VB rises up to the final level VR which is decided by the voltage dividing ratio of the voltage divider as well as the Zener voltage of the diode 4 on the basis of the time constant CR1. The circuit 5 delivers the signal VO while VB<VTH is satisfied. When the power supply is cut, the discharge current of the C3 and the current from the power supply side flow to the resistance R2. Then VB<VTH is assuredly obtained during a drop of VA. Thus the circuit 5 delivers the signal V0.

Description

【発明の詳細な説明】 本発明は、電源の投入、遮断、電圧低下などに際して電
子制御回路に生ずる誤動作もしくは誤不動作を防止する
ためのリセット信号な出力するリセット回路に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit that outputs a reset signal to prevent malfunctions or malfunctions that occur in electronic control circuits when power is turned on, cut off, or voltage drops.

例えばインバータを制御する電子制御回路においては、
電源の投入、遮断、−圧低下などの際、回路動作を正常
に行い得ない状態が生じて誤動作信号を出力し、そのた
め電源に対して直列に接続されている一対のインバータ
アームが同時に導通されることにより電源短絡をひき起
こすおそれがある。インバータ以外においても、例えば
−9のトリップ信号を出力したり、逆に出力すべき信号
を出力しなかったりする場合が生じ得る。このような不
都合を除去するために電子制御回路なり七ッ卜するため
のリセット回路が用いられる。この種のリセット回路の
従来構成例を第1図および第2図に示す。
For example, in an electronic control circuit that controls an inverter,
When the power is turned on, shut off, or when the voltage drops, a situation occurs in which the circuit cannot operate normally and a malfunction signal is output, causing a pair of inverter arms connected in series to the power supply to become conductive at the same time. This may cause a power short circuit. Even in devices other than the inverter, there may be cases where, for example, a trip signal of -9 is output, or conversely, a signal that should be output is not output. In order to eliminate such inconveniences, an electronic control circuit or a reset circuit is used. Examples of conventional configurations of this type of reset circuit are shown in FIGS. 1 and 2.

第1図においては、電源電圧に対して抵抗1とコンデン
サ3を直列にして接続t、直列接続点から取出されるコ
ンデンサ3の端子電圧VBIを判定回路5の第1の入力
信号とし、電源印加点の電圧VAを第2の入力信号とし
て判定回路5に導くものである。
In FIG. 1, a resistor 1 and a capacitor 3 are connected in series with respect to the power supply voltage t, the terminal voltage VBI of the capacitor 3 taken out from the series connection point is used as the first input signal of the judgment circuit 5, and the power supply is applied. The voltage VA at the point is led to the determination circuit 5 as a second input signal.

第2図においては、第1図のコンデンサ3に対して抵抗
2が並列に接続され、抵抗1と抵抗2とで分圧器が構成
されるようにしている。他は第1図の回路と同様である
In FIG. 2, a resistor 2 is connected in parallel to the capacitor 3 of FIG. 1, so that the resistor 1 and the resistor 2 constitute a voltage divider. The rest is the same as the circuit shown in FIG.

第1図、第2図の両者とも電源印加点から取出される第
2の入力信号vAは判定回路5内で適轟な値vTH1例
えば電源電圧の1/2の値に分割されて第1の入力信号
と比較される。
In both FIG. 1 and FIG. 2, the second input signal vA taken out from the power supply point is divided in the judgment circuit 5 into an appropriate value vTH1, for example, 1/2 of the power supply voltage. compared to the input signal.

いま、第1図、第2図の回路に1第3図KvAで示す波
形の電圧が印加されたものとすると、第1図ないし第2
図のコンデンサ3の端子電圧は篤3図K VB 14 
イL VB 2 (定常状Wl テハVB 2 > V
T Hとなるように設定される)で示されているように
、抵抗1の抵抗値B およびコンデンサ3のキャパシタ
ンスC3の積に応じて決まる時定数に従って徐々に上昇
する。判定回路5は電圧vB1.VB2を電圧vTHと
比較し、vBl< v’rl’l t f、=Gt V
B2 <V’rhの範囲でリセット信号vo1(第1図
)ないしV。2(第2図)を出力する。
Now, suppose that a voltage with a waveform shown by 1 KvA in FIG. 3 is applied to the circuits shown in FIGS. 1 and 2.
The terminal voltage of capacitor 3 in the figure is Atsushi 3 K VB 14
IL VB 2 (Steady state Wl Teha VB 2 > V
TH), it gradually increases according to a time constant determined by the product of the resistance value B of the resistor 1 and the capacitance C3 of the capacitor 3. The determination circuit 5 determines the voltage vB1. Compare VB2 with voltage vTH, vBl<v'rl'l t f,=Gt V
Reset signal vo1 (FIG. 1) to V in the range B2 <V'rh. 2 (Figure 2) is output.

このように第1図、第2図の回路では電源投入時に電源
電圧がほぼ定常値(定格値)に達するまで、もしくは定
常値に達して所定時間が経過するまでは、リセット信号
を出して、電子制御回路を正しくリセットする。しかし
、この種の従来回路の欠点は、電!遮断時にはコンデン
サ3に残る電圧のため電圧VB□、VB□の減衰が電圧
vTHの減衰よりも遅れ、したがって、V<V  もし
くハvB2<vTHという状態が生じないので・、リセ
ット信号が生じないことである。%に、この問題は、平
滑回路等を設けていて電暉遮断時の電生低下速度の遅い
電源システムのもとて他の電源システムを制御するよう
な場合に起こる障害に、対、応できないという意味で、
その解決が、望まれていた。
In this way, in the circuits shown in Figs. 1 and 2, when the power is turned on, the reset signal is output until the power supply voltage reaches almost a steady value (rated value) or until a predetermined time has elapsed after reaching the steady value. Properly reset electronic control circuits. However, the drawback of this type of conventional circuit is Due to the voltage remaining in the capacitor 3 at the time of shutoff, the attenuation of the voltages VB□ and VB□ lags behind the attenuation of the voltage vTH. Therefore, the state of V<V or vB2<vTH does not occur, so no reset signal is generated. That's true. %, this problem is caused by a power supply system that has a smoothing circuit, etc., and whose power decreases at a slow rate when the power is cut off, and cannot cope with failures that occur when controlling other power supply systems. In that sense,
A solution was desired.

本発明の目的は、電源の投入時のみならず、遮断時ない
し電圧低下時にも正しく動作するリセット回路を提供す
ることKある。
An object of the present invention is to provide a reset circuit that operates correctly not only when the power is turned on but also when the power is turned off or when the voltage drops.

この目的を達成するために本発明は、電源遮断。To achieve this objective, the present invention provides power interruption.

時ないし、電、圧低下時のために、電源電圧に6些例す
る電圧と比較される電圧を、電源電圧から宥電圧素子を
介して取出てようにしたもの−であり7以下実施例に基
づいて詳細、に説明する。
In case of time or voltage drop, the voltage to be compared with the power supply voltage is extracted from the power supply voltage through a voltage tolerance element. Based on the details, explained in detail.

第4図は本発明の、−実施例を示すものである。FIG. 4 shows an embodiment of the present invention.

この、実施例において、は、抵抗1.2に、よって分圧
器を構平すると共に、電圧印加点A側の抵抗IKに定電
圧菓子としてツェナーダイオード4を直列に接続し、分
圧出力側の抵抗2にコンデンサ3を接続している。電源
電圧VA、、″fなわちツェナーダイオード4、抵抗1
および抵抗2、コンデンサ    3から成る回路にか
かる電圧と、蝙抗2お千びこれに並列のコンデンサ3の
両端電圧vBv判定回路5咳導いている。判定回路5で
は、電圧VBと、電圧vAに比例する電圧vT□とを比
較する0駈VT□は、電圧V、が定常値(定格値)Kあ
る時に、v、TH< vBとなるように設定される。ま
た、図示の例ではVT□−TvAである0判定、−路5
は、v8<−1の時にリセット信号voを出方する◎第
4図の回路において、電源が投、人、されると、第5図
忙示すように、電源電圧vAの上昇に対応して電圧vT
Hが上昇する。電圧VBは電圧V□がツェナ下ダイオ−
、ド4のツェナー電圧v2を超えた時点から増加、し始
める。電圧1の最終到達値嵐は、電源電圧4の定格値V
 V81.抵抗1.2であり、電圧VBI裏この′vR
1で時定数c]lt (ただし、Cはコンデンサ3の中
ヤパシタンス)K従って上昇する。この過程で、VB<
VTHの間判定回路5はリセット信号voを出力する。
In this embodiment, a voltage divider is constructed by the resistor 1.2, and a Zener diode 4 is connected in series as a constant voltage confectioner to the resistor IK on the voltage application point A side, and the resistor on the voltage division output side is Capacitor 3 is connected to 2. Power supply voltage VA, ``f, i.e. Zener diode 4, resistor 1
A voltage applied to a circuit consisting of a resistor 2 and a capacitor 3, and a voltage vBv across the resistor 2 and a capacitor 3 in parallel thereto is conducted to a circuit 5 for determining vBv. The determination circuit 5 compares the voltage VB with the voltage vT□ which is proportional to the voltage vA. Set. In addition, in the illustrated example, the 0 judgment is VT□-TvA, and the -path 5
outputs a reset signal vo when v8<-1. ◎In the circuit shown in Figure 4, when the power is turned on, the voltage VA increases as shown in Figure 5. Voltage vT
H increases. The voltage VB is the voltage V□ which is the diode under Zener.
, starts to increase from the point where it exceeds the Zener voltage v2 of node 4. The final value Arashi of voltage 1 is the rated value V of power supply voltage 4
V81. The resistance is 1.2, and the voltage VBI is this 'vR.
1, the time constant c]lt (where C is the capacitance of the capacitor 3)K therefore increases. In this process, VB<
The VTH period determination circuit 5 outputs a reset signal vo.

次に電源遮断時に電圧VAが値v8から所定の時定数を
もって図示のごとく減衰する場合についそ考える。この
場合、抵抗2には;ンデンサ3の放電電流とツェナーダ
イオード4および抵抗1を介して電源側から供給される
電流とが重畳して流れており、判定回路5への入力信号
となる電圧V、(t 。
Next, consider the case where the voltage VA attenuates from the value v8 with a predetermined time constant as shown in the figure when the power is cut off. In this case, the discharge current of the capacitor 3 and the current supplied from the power supply side via the Zener diode 4 and the resistor 1 are flowing in the resistor 2 in a superimposed manner, and the voltage V which becomes the input signal to the determination circuit 5 is , (t.

(VA −Vz) !’2/ (R、+ R2)<VB
<VA−VZとなる0すなわち、VBは必ずvA−vz
以下となる。vZはほぼ一定の値をとるので、第5図に
示されている工うに、■の降下中に必ずv、 <VTH
ム (−vA/2)となり、そこで判定回路5は再度リセッ
ト信号voを出す@ 第411iIの回路では電源投入時と遮断時の判定回路
入力信号を同一回路で得ているが、両信号を別々の回路
で得ることもできる。その−例を第6図に示す。
(VA-Vz)! '2/ (R, + R2)<VB
<0 which becomes VA-VZ, that is, VB is always vA-vz
The following is true. Since vZ takes a nearly constant value, in the process shown in Fig. 5, v, <VTH must occur during the descent of ■.
(-vA/2), and the determination circuit 5 issues the reset signal vo again.@ In the circuit of No. 411iI, the determination circuit input signals at power-on and power-off are obtained by the same circuit, but both signals are separately generated. It can also be obtained with the following circuit. An example thereof is shown in FIG.

第6図のリセット回路においては、電源投入時用リセッ
ト信号を得るための信号形成回路10として抵抗11と
、これに直列の抵抗12と、この抵抛2に並列のコンデ
ンサ13が設けられ、電源速断時用のリセット信号を得
るための信号形成回路部として、定電圧素子列と、これ
に直列の抵抗nが設けられている0そして抵抗12.2
2の電圧が判定回路15の両入力端子に導かれている0 信号形成回路10は、第2図の場合と全く同様和してリ
セット信号を出力する0この回路10が電源遮断時にリ
セット信号を出力しないことは既に述べた通りである。
In the reset circuit shown in FIG. 6, a resistor 11 is provided as a signal forming circuit 10 for obtaining a reset signal for power-on, a resistor 12 in series with this, and a capacitor 13 in parallel with this resistor 2. As a signal forming circuit section for obtaining a reset signal for fast-acting, a constant voltage element array and a resistor n connected in series with the constant voltage element array are provided.
2 voltages are led to both input terminals of the determination circuit 15.The signal forming circuit 10 sums the sum and outputs a reset signal in exactly the same way as in the case of FIG. As already mentioned, it is not output.

次に信号形成回路部であるが、抵抗ρの電圧vgは、定
電圧素子別の両端電圧なりzとすれば、 VB20 ” vA+ vz ”t”表Jtt、仮ニv2=vTH,+vAとすれば、
電源電圧V□の減衰につれて、電圧VTRおよびηlは
第7図に示″fように変化する0図からも判る通り、V
B2oはV□=vzの時に零となる0電源遮断から、こ
こに到る過程で必ずVB20=vTHとなるので、それ
以降判定回路15はリセット信号光を出す。しかし、回
路部は、電源投入時にはやや早くリセット信号が無くな
ってしまうので、専ら電源遮断時用に用いるのが好まし
い。
Next, regarding the signal forming circuit section, the voltage vg of the resistor ρ is the voltage across each constant voltage element, and if it is z, then VB20 `` vA + vz ``t'' Table Jtt, tentatively d v2 = vTH, +vA. ,
As the power supply voltage V□ attenuates, the voltages VTR and ηl change as shown in FIG.
Since B2o becomes zero when V□=vz, and VB20=vTH in the process up to this point, the determination circuit 15 outputs a reset signal light. However, since the circuit section loses the reset signal rather quickly when the power is turned on, it is preferable to use it only when the power is turned off.

上記各実施例においては、零ボルトを基準とした回路で
あるが、v8電位を基準として極性反転した第9図の1
うな回路構成でも良いことはもちろんである。第9図は
、−例として門4図の回路に適用した場合のものであり
、各符号は第4図のものにそのまま対応する。もちろん
回路動作も全く同様である。
In each of the above embodiments, the circuit is based on zero volts, but the circuit shown in FIG.
Of course, a similar circuit configuration would also work. FIG. 9 shows a case where the circuit is applied to the circuit of FIG. 4 as an example, and each reference numeral corresponds to that of FIG. 4 as is. Of course, the circuit operation is also exactly the same.

以上述べたように本発明によれば、定電圧素子を巧み釦
用いることにエリ、電源電圧遮断時にもリセット信号を
確実忙得ることができるので、遮断時の電源電圧降下速
度の異なる複数の電源回路を持つシステムの制御が容易
になる。また、安価な回路部品な用いながらも、回路定
数の適当な選定にエリ、電源電圧投入時の立上りの遅い
システムでも確実にリセット信号を得ることができる。
As described above, according to the present invention, by skillfully using a constant voltage element, it is possible to reliably obtain a reset signal even when the power supply voltage is cut off. It becomes easier to control systems with circuits. In addition, even though inexpensive circuit components are used, by appropriately selecting circuit constants, a reset signal can be reliably obtained even in a system where the power supply voltage rises slowly when turned on.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は、従来の異なるリセット回路を示
す結線図、 第3図は4第1図および第2図の回路の動作特性を示す
線図、 第4図は、本発明の一実施例を示す結線図、第5図は、
第4図の回路の動作特性を示す線図、第6図は、本発明
の他の実施例を示す結線図、第7図鰺會伊蛭今台は、第
6図の回路の動作特性を示す線図、 第3図は、本発明のさらに他の実施例を示す結線図であ
る。 1 、2.11.12.薦・・・抵抗、3.13・・・
コンデンサ、4・・・ツェナーダイオード、U・・・定
電圧素子、5.15・・・判定回路。 出願人代理人   猪  股     清第4 囚  
   6″6図 啼間□ 躬 7 図 躬 8 囚 手続補正書 昭和圀年り月/V−日 特許庁長官   島 1)春 樹殿 1、事件の表示 昭和圀年特許願第118029号 2、発明の名称′ り七ット回路 3、補正をする者 事件との関係特許出願人 (307)東京芝浦電気株式金社 明細書の「発明の詳細な説明」の―、および図面8、補
正の内容 (1)  明細書中、第8頁第7行の「判定回路」の前
krNAND回路から成る」を加入する。 (2)  同、第8頁第16行の「仮k」の前に「電源
電圧−が定格値にある時に」を加入する。 (3)  WJ画面中第6図を別紙の通りに訂正する。 以上
1 and 2 are connection diagrams showing different conventional reset circuits, FIG. 3 is a diagram showing the operating characteristics of the circuits shown in FIGS. 1 and 2, and FIG. The wiring diagram illustrating the embodiment, FIG. 5, is as follows:
Figure 4 is a diagram showing the operating characteristics of the circuit, Figure 6 is a wiring diagram showing another embodiment of the present invention, Figure 7 is a diagram showing the operating characteristics of the circuit in Figure 6. FIG. 3 is a wiring diagram showing still another embodiment of the present invention. 1, 2.11.12. Recommendation...Resistance, 3.13...
Capacitor, 4... Zener diode, U... Constant voltage element, 5.15... Judgment circuit. Applicant's Representative Kiyoshi Inomata 4th Prisoner
6″6 Diagram □ 7 Diagram 8 Prison procedure amendment Showa Kuni Year/V-day Commissioner of the Patent Office Shima 1) Haru Judono 1, Indication of the case Showa Country Patent Application No. 118029 2, Invention Name of ``Detailed Description of the Invention'' in the patent applicant (307) Tokyo Shibaura Electric Co., Ltd. Specification related to the person making the amendment, Seven Circuits 3, and Drawing 8, Contents of the amendment (1) In the specification, add "consisting of a krNAND circuit" in front of "judgment circuit" on page 8, line 7. (2) Add "when the power supply voltage - is at the rated value" before "temporary k" on page 8, line 16. (3) Correct Figure 6 on the WJ screen as shown in the attached sheet. that's all

Claims (1)

【特許請求の範囲】 1、電源電圧から定電圧素子を介して得られる電圧に比
例する電圧を出力する電圧信号回路と、この電圧信号回
路の出力電圧を定常時にこれよりも低くなるように設定
されpJIL#1電圧に比例する電圧と比較し、前者が
後者よりも低いときにリセット信号を出力する判定回路
とを備えて成るリセット回路。 2、電源に接続された、定電圧素子細よび分圧器の直列
回路、ならびに前記分圧器の分圧出力側分圧器素子に並
列に接続された;ンデンサから成る電圧信号回路と、こ
の電圧信9回路の出力電圧を定常時にこれよりも低くな
るように設定された、電源電圧に比例する電圧と比較し
、前者が後者よりも低いときにリセット信号を出力する
判定回路とを備えて成るり七ツ)1回路。 3、電源電圧を分圧する分圧器およびその分圧器の分圧
出力側分圧器素子に並列に接続されたコンデンサから成
る第1の電圧信号回路と、電源電圧から定電圧素子を介
して得られる電圧に比例する電圧を出力する第2の電圧
信号回路と、前記第1の電圧信号回路および第2の電圧
信号回路の各出力電圧を定常時にこれよりも低くなるよ
うに設定された電源電圧に比例する電圧と比較し、前者
が後者よりも低いと龜にリセット信号を出力する判定回
路とを備えて成るリセット回路。
[Scope of Claims] 1. A voltage signal circuit that outputs a voltage proportional to the voltage obtained from the power supply voltage via a constant voltage element, and the output voltage of this voltage signal circuit is set to be lower than this during normal operation. and a determination circuit that compares the pJIL#1 voltage with a voltage proportional to the pJIL#1 voltage and outputs a reset signal when the former is lower than the latter. 2. A voltage signal circuit consisting of a constant voltage element connected to a power supply, a series circuit of a voltage divider, and a capacitor connected in parallel to the voltage divider element on the output side of the voltage divider; and a determination circuit that compares the output voltage of the circuit with a voltage proportional to the power supply voltage that is set to be lower than this during steady state, and outputs a reset signal when the former is lower than the latter. TS) 1 circuit. 3. A first voltage signal circuit consisting of a voltage divider that divides the power supply voltage and a capacitor connected in parallel to the voltage divider element on the output side of the voltage divider, and a voltage obtained from the power supply voltage through the constant voltage element. a second voltage signal circuit that outputs a voltage proportional to the output voltage of the first voltage signal circuit and the second voltage signal circuit, and a second voltage signal circuit that outputs a voltage proportional to and a determination circuit that outputs a reset signal to the terminal when the former is lower than the latter.
JP11802981A 1981-07-28 1981-07-28 Resetting circuit Pending JPS5820032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11802981A JPS5820032A (en) 1981-07-28 1981-07-28 Resetting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11802981A JPS5820032A (en) 1981-07-28 1981-07-28 Resetting circuit

Publications (1)

Publication Number Publication Date
JPS5820032A true JPS5820032A (en) 1983-02-05

Family

ID=14726291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11802981A Pending JPS5820032A (en) 1981-07-28 1981-07-28 Resetting circuit

Country Status (1)

Country Link
JP (1) JPS5820032A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051842A (en) * 1983-08-31 1985-03-23 Fuji Xerox Co Ltd Destaticizer in common use as light shielding plate of copying machine
JPS60138527A (en) * 1983-12-27 1985-07-23 Fuji Xerox Co Ltd Light shielding device of copying machine
US4634905A (en) * 1985-09-23 1987-01-06 Motorola, Inc. Power-on-reset circuit having a differential comparator with intrinsic offset voltage
JPS62203174A (en) * 1986-03-03 1987-09-07 Hiromu Asada Fine electrophotographic method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6051842A (en) * 1983-08-31 1985-03-23 Fuji Xerox Co Ltd Destaticizer in common use as light shielding plate of copying machine
JPS60138527A (en) * 1983-12-27 1985-07-23 Fuji Xerox Co Ltd Light shielding device of copying machine
US4634905A (en) * 1985-09-23 1987-01-06 Motorola, Inc. Power-on-reset circuit having a differential comparator with intrinsic offset voltage
JPS62203174A (en) * 1986-03-03 1987-09-07 Hiromu Asada Fine electrophotographic method

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