JPS58195339A - Signal transmitting device - Google Patents

Signal transmitting device

Info

Publication number
JPS58195339A
JPS58195339A JP57079471A JP7947182A JPS58195339A JP S58195339 A JPS58195339 A JP S58195339A JP 57079471 A JP57079471 A JP 57079471A JP 7947182 A JP7947182 A JP 7947182A JP S58195339 A JPS58195339 A JP S58195339A
Authority
JP
Japan
Prior art keywords
pulse
level
diode
output
zener
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57079471A
Other languages
Japanese (ja)
Inventor
Akitoshi Yoshizaki
吉崎 有香
Shinichiro Hayashi
伸一郎 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP57079471A priority Critical patent/JPS58195339A/en
Publication of JPS58195339A publication Critical patent/JPS58195339A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/38Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40Transmitting circuits; Receiving circuits
    • H04L25/49Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/493Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Abstract

PURPOSE:To improve noise resistance, by receiving the 1st and the 2nd pulses having different synchornizing ''1'' level of front and tail ridges of a transmission signal and extracting a pulse signal within a permissible level range at the reception side. CONSTITUTION:A conversion circuit 11 generates pulses P11, P12 which are in synchornization with the front and tail ridges of the transmission signal P and transmits pulses P100 and P50 of levels 2E and E. When the pulse P100 is received, diodes 403, 503 and 504 having <=EV of the Zener potential are conductive and a bistable multivibrator 600 produces an output. On the other hand, a TR 501 is turned off and no input is given to the bistable multivibrator 600. When the pulse P50 is received, it pases through the Zener diode 503 only, a TR 502 only is turned on and the output of the bistable multivibrator 600 disapperars. Thus, a signal P is extracted from the bistable multivibrator 600. When the reception pulse is higher than the Zener diode of the diode 404, the bistable multivibrator 600 produces no output. When the reception pulse is lower in level than the Zener potential of the diode 504, all the Zener diodes are cut off.

Description

【発明の詳細な説明】 この開明は、パルス信号の信号伝達装置に関する。[Detailed description of the invention] This disclosure relates to a signal transmission device for pulse signals.

第1因に、この柚の信号伝達装置の従来例を示す。図に
おいて、10は兄侶仙であって、送信すべき信号Pのレ
ベルに応答してスイッテンク動作するスイッチング菓子
(トランジスタ)11の出力パルスP、。を伝送路20
に送dする。12.13は電流制限抵抗、Eはm動電源
の電圧である。30え、該スイッチング素子31の入力
回路に、抵抗32とコンデンサ33からなるフィルタを
介して出刃パルスP+nを受け、スイッチング素子31
のコレクタから受信出力Pillが取出される。34.
35は一流制限抵抗、Xは上記入力回路とフィルタの接
続点である。
The first factor is a conventional example of this Yuzu signal transmission device. In the figure, reference numeral 10 indicates an output pulse P of a switching device (transistor) 11 that performs a switching operation in response to the level of a signal P to be transmitted. The transmission line 20
Send to. 12.13 is a current limiting resistor, and E is the voltage of the m dynamic power source. 30, the input circuit of the switching element 31 receives the blade pulse P+n through a filter consisting of a resistor 32 and a capacitor 33, and the switching element 31
The received output Pill is taken out from the collector. 34.
35 is a first-class limiting resistor, and X is a connection point between the input circuit and the filter.

この構成では、受@14113Gの入力回路にフィルタ
ケ設けて、伝送路20から侵入するノイズを防ぐよ5K
しているが、抵抗32とコンデンサ33のフィルタの時
定数が小さい場合には上記接続点Xの電位が上昇する恐
れがあり、一般に、トランジスタのベース・エミッタ間
電圧は非常に低いので、上dじ恢わC点Xの電位の上昇
により計!ランジスタロ1かオン動作して受911tl
力Ps・が誤匍号となる欠点かある。勿緬、上とフィル
タの時定数を大きく丁れはこり欠点が緩和されるがそれ
だけ91勺の導通が遅くなる欠点かあった。又、耐ノイ
ズ性を尚めるAKは伝送エネルギーを大きくすれはよい
が経崎面から好ましくない。
In this configuration, a filter is installed in the input circuit of the receiver@14113G to prevent noise from entering from the transmission line 20.
However, if the time constant of the filter of resistor 32 and capacitor 33 is small, there is a risk that the potential at the connection point Calculated by the gradual rise in potential at point C! Ranjistaro 1 turns on and receives 911tl
There is a drawback that the force Ps is incorrect. Of course, by increasing the time constant of the filter, this problem can be alleviated, but there is also the drawback that the conduction of the 91-pin becomes slower. Also, for AK which improves noise resistance, it is possible to increase the transmission energy, but this is not preferable from the economic point of view.

この発明は、上記した従来のものの欠点を除去第2パル
スを受gIIUnに送り、受毎−jで、両パルスが、両
パルスに対して夫々予め設定これた許容レベル帷囲内に
あるか否〃≧を検出し℃許容レベル岬囲内にあるjIA
台パルス発生回路を駆動してパルス1d号を取り出す構
成とすることにより、従来に比して耐ノイズ性に丁ぐれ
fi! IFJ性が4<、n[のよ、′□。
The present invention eliminates the above-mentioned disadvantages of the prior art.The present invention sends the second pulse to the receiver gIIUn, and checks whether both pulses are within a preset tolerance level range for each pulse at each reception -j. JIA that detects ≧ and is within the ℃ tolerance level cape
By driving the base pulse generation circuit and extracting the pulse No. 1d, it has better noise resistance than conventional fi! IFJ personality is 4<, n[noyo,'□.

いfg ′f5伝璋を有うことかで、、きる信号伝達装
噴を提供″′fることを目的とする。
The purpose of the present invention is to provide a signal transmission system that can transmit signals by having a fg 'f5 transmission.

以f1このxA明の一実施例を図について説明する。An embodiment of this xA light will now be described with reference to the drawings.

第2図にお9て、101は送信l111変侠回路で、込
侶丁べき信号Pの曲縁に同期した狭巾のパルスpHと後
縁に同期した狭巾のパルスp1tを発生する回w!11
00から該パルスpH、pHを受ける。
In FIG. 2, reference numeral 101 denotes a transmission l111 variable circuit, which generates a narrow pulse pH synchronized with the curved edge of the signal P and a narrow pulse p1t synchronized with the trailing edge of the signal P. ! 11
00 to receive the pulse pH and pH.

102及び103はスイッチング素子であるトランジス
タであって、夫々のペースにパルスpH及びPllか入
力される。104は込fgIIllパルス俊圧器であっ
て、−次巻線105の中間点Cにトランジスター02の
コレクタが僧幌され、巻終り狽11端(按地倹1端)に
トランジスター03のコレクタが汝4i 8れており、
トランジスター02及び103か夫々パルスpH及びP
、を受けて導通すると、レベル2Eの第1パルスPI0
6 及びレベルEの第2パルスP嘗・を、二次巻Iwi
!106から伝送路200に送出する。 。
102 and 103 are transistors which are switching elements, and pulse pH and Pll are input to each pace. 104 is a fg IIll pulse pressure regulator, in which the collector of the transistor 02 is connected to the intermediate point C of the second winding 105, and the collector of the transistor 03 is connected to the end of the winding 11 (the first end of the winding). 8 and
Transistors 02 and 103 respectively pulse pH and P
, the first pulse PI0 of level 2E
6 and the second pulse P of level E, the secondary winding Iwi
! 106 to the transmission line 200. .

、′ 300は受!!側パルス変圧器であって、伝送路200
に接続、1された一次巻#3o1と、2つ。ユ″11 次巻線30L 30Bを有している。400は二次巻脚
302から人力を受ける第1のレベル検i路、 λ50
0は二次巻#1303から入力を受ける第2のレベル構
出1!fil!i!r、601〜:1マルチ)である、
)@lのレベル検出回w6400はトランジスタ401
ト402を具え、トランジスタ4010ベース1路には
定電圧ダイオード403と入力抵抗405が挿入in、
  トランジスタ4020ペース回路には定電圧ダイオ
ード404と入力抵抗406が挿入され℃おり、トラン
ジスタ402のコレクタはダイオード401を介してト
ランジスタ401のベースに接続され℃いる。、定電圧
ダイオード404及び403は第1パルスpHl@に対
するff容レベル範囲の上限レベル及び下限レベルを夫
々設定する鳥のもので、例えば、E=100ボルトであ
る礪せには夫々110ボルト及び9.0ボルトのツェナ
ー電位を持たせる。トランジスタ402のコレクタ出力
は極性反転の為のインバータ40Bを介し℃双安定マル
チ600のセット端子Sに入力される。′@20レベル
検出沖1路500においz、501及び502はトラン
ジスタ、503及び504は定″wlL比ダイオード、
505及び506は入力抵抗、50りはダイオード、5
08はインバータである。
,' 300 is received! ! A side pulse transformer, the transmission line 200
Connected to, 1 primary volume #3o1 and 2. The unit has primary windings 30L and 30B. 400 is the first level test path which receives human power from the secondary winding leg 302;
0 is the second level configuration 1 that receives input from secondary volume #1303! fil! i! r, 601~:1 multi),
)@l level detection circuit w6400 is transistor 401
A constant voltage diode 403 and an input resistor 405 are inserted in one path of the base of the transistor 4010.
A constant voltage diode 404 and an input resistor 406 are inserted into the transistor 4020 pace circuit, and the collector of the transistor 402 is connected to the base of the transistor 401 via the diode 401. , constant voltage diodes 404 and 403 are used to set the upper and lower limit levels of the ff capacitance level range for the first pulse pHl@, respectively.For example, for E=100 volts, 110 volts and 9 It has a Zener potential of .0 volts. The collector output of the transistor 402 is input to the set terminal S of the °C bistable multi 600 via an inverter 40B for polarity inversion. '@20 level detection Oki 1 path 500, 501 and 502 are transistors, 503 and 504 are constant"wlL ratio diodes,
505 and 506 are input resistors, 50 is a diode, 5
08 is an inverter.

定電ダイオード503及び504は@2パルスPI(+
に対する許容レベル軸1の上限レベル及び下限レベルを
夫々設定する為のもので、上記のようにE−100ボル
トである場せ、例えは夫々60ボルト及び40ボルトの
ツェナー電位を持たせる。トランジスタ502のコレク
タ出力はパルス発生回路(双安寛マルチ)6θ0のリセ
ット端子Rに入力される。
Constant voltage diodes 503 and 504 @2 pulse PI (+
This is for setting the upper limit level and lower limit level of the tolerance level axis 1, respectively.As mentioned above, if the voltage is E-100 volts, for example, the Zener potentials are set to 60 volts and 40 volts, respectively. The collector output of the transistor 502 is input to the reset terminal R of the pulse generation circuit (Hiroshi Soyasu multi) 6θ0.

次に、この@置の動作について説明する。Next, the operation of this @ position will be explained.

今、電圧Eが100ボルトであるとする。第1パルスP
、・・が受gsIlllに到米すると、ツェナー電位が
100ボルト以上である定電圧ダイオード404を除く
他の定電圧ダイオード403.503.504が導通す
る。この為、トランジスタ401がオンし、双安定マル
チ600が出力する。他方、トランジスタ501&C流
入しようとするペース電流はダイオード501を介して
トランジスタ501 KfitLる為、トランジスタ5
01はオフし、双安定マルテ600のリセット端子Rに
は入力されない。
Suppose now that the voltage E is 100 volts. 1st pulse P
, . Therefore, the transistor 401 is turned on and the bistable multi 600 outputs. On the other hand, the pace current that attempts to flow into the transistors 501&C flows through the diode 501 to the transistors 501 and 501.
01 is turned off and is not input to the reset terminal R of the bistable malte 600.

続いて、第2パルスP、・0が受信側に到米すると、ツ
ェナー電位が50ボルト以下である定電圧ダイオード5
03を通過するが他の定電圧ダイオード403.404
.504 では阻止される。この為、トランジスタ50
2だけがオンし、双安定マルチ600のリセット端子R
にトランジスタ502の出力が入力きnるので、双安定
マルチ600の出力は消めつする。か(して、m号Pが
双安定マルチ600から取出される。
Subsequently, when the second pulse P, 0 reaches the receiving side, the constant voltage diode 5 whose Zener potential is 50 volts or less
03 but other constant voltage diodes 403.404
.. 504 is blocked. For this reason, the transistor 50
Only 2 is turned on, and the reset terminal R of the bistable multi 600
Since the output of the transistor 502 is input to the input signal, the output of the bistable multi 600 is turned off. (Thus, the m number P is taken out from the bistable multi 600.

受4M ’11111に到来したパルスが定電圧ダイオ
ード404のツェナー電位より商い場合にはトランジス
タ401のベースに流れようとする電流がダイオード4
01を介してトランジスタ402に流れる為、トランジ
スタ401はオフ、シ、双安定マルチ600は出力しな
い。定電圧ダイオード504β のツェナー電位より低レベルのパー、1.ルスが受信1
ull K51J米した礪せには、全ての足電圧、′、
、ダイオード403404.503.504#、C71
Qカフ?♀:′1′1い5.つ2ツスタ401.402
.501.502はいずれもオンしない。
If the pulse that has arrived at the receiver 4M'11111 is lower than the Zener potential of the constant voltage diode 404, the current that is about to flow to the base of the transistor 401 is
Since the current flows to the transistor 402 via the transistor 01, the transistor 401 is off, the bistable multi 600 does not output. A level lower than the Zener potential of the constant voltage diode 504β, 1. Luz received 1
ll K51J rice has all foot voltages,',
, diode 403404.503.504#, C71
Q cuff? ♀:'1'15. 401.402
.. 501 and 502 are not turned on.

以上の如く、この発明によれば、送るべき信号の前縁と
f&41に夫々同期しレベルの異る第1・及び第2パル
スを受mi1+に送り、受信側では、入力がil及び第
2パルスに対して夫々設定さnた許容レベル範曲内にあ
る場合に出力してパルス発生回路をセット・リセットす
る2つのレベル検出(ロ)路で到来したパルスをチェッ
クする構成としたことにより、上dC許許容しル動囲外
にあるパルスが受18i1111に到来しても応答しな
いので、ph賛伝込エネ面す ルギーを大きくすることな(従来に比して、秦ノイズ性
を^め、91号伝達の稍激及び1!幀性の^い侶勺伝達
V装置を得ることができる。
As described above, according to the present invention, the first and second pulses having different levels are sent to the receiver mi1+ in synchronization with the leading edge of the signal to be sent and f&41, respectively, and on the receiving side, the input is il and the second pulse. By having a configuration in which the incoming pulse is checked by two level detection (b) paths that output and set/reset the pulse generation circuit when the pulse is within the allowable level range set respectively for the above. Even if a pulse outside the dC allowable motion range arrives at the receiver 18i1111, it will not respond, so there is no need to increase the ph input energy (compared to the conventional method, there is less noise) It is possible to obtain a transmission V device with a very strong No. 91 transmission and a 1!

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の信号伝−i!装置の回路図、@2図はこ
の発明による信号伝達i*の実施例の回路図である。 図において、1 G 、l、、・・・変換回路、102
.103・・・スイッチング素子1、、ij、。 104°−7< A−2変圧器゛゛; 200・・・伝送路、  300・・・パルス変圧器、
400・・・mlのレベル検出回路、 401、402 ・・・スイッチング素子、403.4
04・・・定電圧ダイオード、500・・・第2のレベ
ル検出回路、 501.502・・・スイッチング素子、503.50
4・・・定電圧ダイオード600・・・双女冗マルチ パルス兜生回に@。 なお、回申、同一符号は同−又は相当部分を示す0 代理人  葛 野 侶 −
Figure 1 shows the conventional signal transmission-i! Circuit diagram of the device, Figure @2 is a circuit diagram of an embodiment of the signal transmission i* according to the invention. In the figure, 1 G, l, . . . conversion circuit, 102
.. 103...Switching element 1,, ij,. 104°-7<A-2 transformer゛゛; 200...transmission line, 300...pulse transformer,
400...ml level detection circuit, 401, 402... switching element, 403.4
04... Constant voltage diode, 500... Second level detection circuit, 501.502... Switching element, 503.50
4... Constant voltage diode 600... @ for the double multi-pulse helmet regeneration. In addition, the same reference numerals in the circular indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 送信すべきm号の曲縁及び後縁に夫々同期する第1のレ
ベルを持つ第1パルス及び第2のレベルを持つ第2パル
スを伝送路に送出する変換(ロ)路、受信側にあって上
記第1及び第2パルスの両者を受ける第1のレベル検出
回路及び第2のレベル検出回路、この第1のレベル検出
回路及び第2のレベル検出回路の出力で夫々セット争リ
セットされるパルス発生回路を具え、上記第1のレベル
検出回路及び第2のレベル検出回路が、夫々、上記第1
パルスに対してあらかじめ設定された許容レベル範囲内
及び第2パルスに対して予め設定された計容レベル伸曲
内にある入力に応答して出力することを%徴とする信号
伝達装置。
A conversion (b) path for sending out a first pulse having a first level and a second pulse having a second level synchronized with the curved edge and trailing edge of the m number to be transmitted, respectively, to the transmission path; a first level detection circuit and a second level detection circuit that receive both the first and second pulses; a pulse that is reset by the output of the first level detection circuit and the second level detection circuit, respectively; a generating circuit, the first level detection circuit and the second level detection circuit each having a
A signal transmission device characterized by outputting in response to an input that is within a preset tolerance level range for the pulse and within a preset metering level extension for the second pulse.
JP57079471A 1982-05-10 1982-05-10 Signal transmitting device Pending JPS58195339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57079471A JPS58195339A (en) 1982-05-10 1982-05-10 Signal transmitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57079471A JPS58195339A (en) 1982-05-10 1982-05-10 Signal transmitting device

Publications (1)

Publication Number Publication Date
JPS58195339A true JPS58195339A (en) 1983-11-14

Family

ID=13690796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57079471A Pending JPS58195339A (en) 1982-05-10 1982-05-10 Signal transmitting device

Country Status (1)

Country Link
JP (1) JPS58195339A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0152246A2 (en) * 1984-02-03 1985-08-21 Rosemount Limited Electrical isolation circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119910A (en) * 1974-08-09 1976-02-17 Nippon Telegraph & Telephone
JPS5693456A (en) * 1979-11-03 1981-07-29 Licentia Gmbh Method and device for transmitting digital signal using signal generator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119910A (en) * 1974-08-09 1976-02-17 Nippon Telegraph & Telephone
JPS5693456A (en) * 1979-11-03 1981-07-29 Licentia Gmbh Method and device for transmitting digital signal using signal generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0152246A2 (en) * 1984-02-03 1985-08-21 Rosemount Limited Electrical isolation circuit
EP0152246B1 (en) * 1984-02-03 1993-03-24 Rosemount Limited Electrical isolation circuit

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