JPS58190065A - Floating gate type nonvolatile memory device - Google Patents

Abstract

PURPOSE:To obtain a floating gate type nonvolatile memory device wherein writing efficiency is favorable by decreasing the drain voltage at the time of write and the integration degree is high by a method wherein the interval between the source and drain of single-layer gate MOS transistor constituted in parallel is formed wide. CONSTITUTION:The first polycrystalline Si film serving as a floating gate 4 is so formed that at least one of right and left edges not on the source and drain sides of the floating gate 4 is positioned on a channel. A control gate 6, the second gate insulation film 5, the flating gate 4, and the first gate insulation film 3 are successively etching-removed, and thus the partial interval L1 between the source and drain of the channel region 10 wherein the floating gate 4 exists is formed smaller than the interval L2 between the source and drain of a chennel 11 wherein this floating gate 4 does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate nonvolatile memory device.

The schematic configuration of a conventional memory device of this type is shown in Figure 1 (
, ) , (b) In each of these figures, (1) is a silicon semiconductor substrate, and (2) is a relatively thick silicon oxide film for isolation between elements (hereinafter abbreviated as field insulating film). , (3) is a relatively thin gate silicon oxide film (hereinafter referred to as the first gate insulating film) formed on the substrate (1), and (4) is a first gate insulating film whose periphery is covered with an insulator to become a floating gate. A polycrystalline silicon film (hereinafter referred to as a floating gate), (5) is formed on this floating gate (4), and a relatively thin gate silicon oxide film (hereinafter referred to as a second gate insulating film), (6) is a second polycrystalline silicon film (hereinafter abbreviated as control gate) formed on the upper surface including the second gate insulating film (5) and serving as a control electrode;
) is an impurity diffusion region of the opposite conductivity type to that of the substrate (1), which becomes the source and drain, and (8) is a field insulating film (
2) The floating gate extension extending above (9) is an interlayer insulating film covering the upper part thereof.

In the above structure, information is written by charging the floating gate (4) with electrons, and data is erased by emitting electrons from the floating gate (4).

In other words, in the process of saving, a relatively high voltage is simultaneously applied to the drain (7) and the control gate (6) to cause avalanche in the drain/nearby channel area to generate high-energy electrons. A part of the floating gate (4) is caused to cross the energy gap of the forbidden band of the first gate insulating film (3) and reach the floating gate (4) by the high voltage electric field applied to the control gate (6). ) The floating gate (
4) Release the electrons in the floating gate (4). At this time, the presence or absence of electrons in the floating gate (4) depends on the difference in the threshold voltage of the memory transistor as seen from the control gate (6). This is what we do.

However, in this conventional configuration, in order to reduce the memory cell area, at least one of the edges of the floating gate (4) on the side opposite to the source and drain (7) is located on the channel. When a floating gate non-volatile MOS transistor with a common gate electrode, source and drain is formed in parallel with a partially gated MOS transistor, writing to the floating gate non-volatile MOS transistor is performed in this state. However, the gate MOS transistor also suffers from avalanche at the same time, resulting in a decrease in drain voltage and a deterioration in the single input efficiency.

In view of these drawbacks of the conventional technology, the present invention has been developed to
, the gap between the source and drain of the gate MOS transistor is widened to reduce the drain voltage during writing, thereby achieving high writing efficiency and high integration floating gate type nonvolatile memory device B- Provide fJ(t,
This is what we are trying to do.

2 (,), (
FIG. 2(a)*(b) shows an apparatus according to an embodiment of the present invention, which will be described in detail with reference to FIGS. In this embodiment, first, a relatively thick field insulating film (2) is formed on a silicon semiconductor substrate (1), and holes are formed by etching away the source, drain and channel regions using photolithography. The surface of the substrate (1) in the opening is oxidized to form a relatively thin first gate insulating film (3).
form.

Next, a first polycrystalline silicon film that will become the floating gate (4) is generated, and the same side of the floating gate (4) is etched away using photolithography to determine the width of the left and right sides of the floating gate other than the source and drain sides. At least one of the left and right edges of the gate (4), which are not on the source or drain side, is formed so as to be located on the channel.

Next, a relatively thin second gate insulating film (5) and a second polycrystalline silicon film that will become the control gate (6) are produced and then processed using photolithography to determine the spacing between the source and drain. , l:9 control gate (6), second gate insulating film (5), floating gate (4), and first gate insulating film (3) are all sequentially etched away by self-aligned etching. Source and drain spacing (I, +
)k, this floating gate (4) does not exist;
floating gate (4) on the channel from the area determined by
The distance (I4) to the edge requires a mask alignment margin of at least about 1 μm or more.

Further, impurities having a conductivity type opposite to that of the substrate (1) are diffused to form a source and a drain (7).

An interlayer insulating film (9) etc. is formed between the gate electrode and the aluminum wiring, and in this embodiment of the floating gate type non-volatile MOS memory device constructed in this way,
As one memory cell, a floating gate type nonvolatile MOS transistor and a single-layer gate MOS transistor form a parallel circuit in which the gate electrode, source, and drain are all common.

Normally, in a MOS transistor, one of the factors that determines the occurrence of avalanche in the ON state is the distance between the source and drain, and as this distance becomes smaller, the electric field strength between the source and drain increases, causing avalanche. It becomes easier. In the device of the above embodiment, a relatively high voltage is simultaneously applied to the drain (7) and the control gate (6) at the same time as in the conventional case, but the voltage actually applied to the drain is applied in parallel. The source-drain spacing (Lx)'ir is determined to be wide enough to prevent the provided partially gated MOS transistor from causing avalanche. However, if the spacing between the source and drain of the channel region where the floating gate (4) exists is also formed to be the same as the spacing between the source and drain (Ls) of the single-layer gate MOS transistor, even if the spacing between the source and drain in the channel region under the floating gate (4) is Since avalanche does not occur and writing is rarely performed, it is recommended to narrow the distance between the source and drain (Ls) in a part of the channel region where this floating gate (4) exists.
This is done by generating an avalanche.

In addition, the gate voltage (VD) in the omitted state in which the floating gate (4) is charged with electrons and in the erased state in which there are no electrons;
FIG. 3 shows the relationship between the source and drain currents (Iam). In this Figure 3, (A) is the floating gate (4)
■) is a state in which there is no electron, and (■) is a state in which there is an electron in (
There is a curved point in the middle of both A, I, and B, but this is because the floating gate nonvolatile MOS transistor and the single-gate MOS transistor are connected in parallel.

Here, we designed the threshold voltage of the floating gate non-volatile MOS transistor in the erased state to be the same as the threshold voltage of the single-layer gate MOS transistor, i, t"ix, and Therefore, by setting a certain gate voltage (vu), data can be stored using two different source-drain currents (Ids).

Note that in the embodiment, the source of the floating gate (4),
Although we have described the case where both the left and right edges that are not on the drain side are located on the channel, as in another embodiment shown in FIG. Only one of them may be located on the channel.

That is, in this embodiment of FIG. 4, the same reference numerals as in the embodiment of FIG. a distance B,) from the region where the source is located to the edge located on the channel but not on the source or drain side;
Floating gate (4) located on field insulation film (2)
The distance (L4) from the edge other than the source/drain side to the edge of the field insulating film (2) requires a mask alignment margin of at least about 1 μm as described above. Also in the embodiment shown in FIG. 4,
According to the present invention, at least one of the left and right edges on the source and drain sides of the floating gate must be located on the field insulating film. Because I configured it so that there is no
It has the advantage of not only improving writing efficiency but also reducing the area of the floating gate and improving the degree of device integration.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are plane views of a floating gate nonvolatile memory device according to a conventional example Vc, and a plane view of a floating gate nonvolatile memory device according to a conventional example Vc, and
Fig. 2(a) is a sectional view of the section line b; cross section,
Figure 3 shows the same Va-Ida characteristics as shown in Figure 4 (
Figures a) and (b) are plan views showing other embodiments of the same as the above, and cross-sectional views taken along the line b-IVb. (1)...Silicon semiconductor substrate, (2)...Field insulating film, (4)...Floating goo), (6)...
... control gate, (7) ... impurity sales area for sources and drains. Agent Ishino - Figure 2 Figure 3

Claims (1)

[Claims] Either overlap at least one of the edges of the floating gate that is not on the source or drain side with the edge of the field insulating film, or
Or, in addition to being located on the channel, the source of the floating gate located over the edge of this field insulating film, or the source and drain spacing at the edge portion other than the drain side, is also located in the area where the floating gate exists. What is claimed is: 1. A floating gate nonvolatile memory device characterized in that at least part of the distance between the source and the drain is formed narrowly.