JPS58183A - Manufacturing method for semiconductor device - Google Patents

Manufacturing method for semiconductor device

Info

Publication number
JPS58183A
JPS58183A JP56098604A JP9860481A JPS58183A JP S58183 A JPS58183 A JP S58183A JP 56098604 A JP56098604 A JP 56098604A JP 9860481 A JP9860481 A JP 9860481A JP S58183 A JPS58183 A JP S58183A
Authority
JP
Japan
Prior art keywords
channel
formation
oxide films
electrode
covered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56098604A
Other languages
Japanese (ja)
Inventor
Masahiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP56098604A priority Critical patent/JPS58183A/en
Publication of JPS58183A publication Critical patent/JPS58183A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To obtain a highly integrated, shallow diffused layer by a method wherein a well region on a semiconductor substrate and a region on the substrate lacking such are divided by a field oxide film and the surfaces of the respective regions are provided with gate electrodes across gate oxide films, and the gate oxide films act as masks for the formation of channel regions, and the channel regions are formed by diffusion. CONSTITUTION:A P<-> type well region 202 is diffusedly formed in an N type semiconductor substrate 201 and the resultant PN junction exposed on the surface of the substrate 201 and a part of the portion lacking a PN junction are respectively covered with thick field oxide films 203. Thin gate oxide films 204 are provided to respectively cover the surfaces surrounded by the films 203, and the central portion is provided with a polycrystalline Si made gate electrode 205. They are alternately covered with a mask 206 exemplifiedly of resist for the application of an impurity for the formation of a P channel and an N channel 207. After this, only the superficial layer of the electrode 205 is oxidated for the formation of an oxide film 208 and the entire surface including the film 208 is covered with an oxide film 210. A window is provided and each channel 207 is provided with an Al electrode 212 across a polycrystalline Si layer 209.
JP56098604A 1981-06-25 1981-06-25 Manufacturing method for semiconductor device Pending JPS58183A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56098604A JPS58183A (en) 1981-06-25 1981-06-25 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56098604A JPS58183A (en) 1981-06-25 1981-06-25 Manufacturing method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS58183A true JPS58183A (en) 1983-01-05

Family

ID=14224203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56098604A Pending JPS58183A (en) 1981-06-25 1981-06-25 Manufacturing method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS58183A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739544A (en) * 1980-08-20 1982-03-04 Towa Seimitsu Kogyo Kk Arranging equipment of semiconductor frame
JPS62154777A (en) * 1985-12-27 1987-07-09 Toshiba Corp Semiconductor device
JPS63131564A (en) * 1986-11-21 1988-06-03 Toshiba Corp Protective circuit for output

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5191675A (en) * 1975-02-07 1976-08-11
JPS51126055A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Contact part formation method in semi-conductor accumulation circuit
JPS51134566A (en) * 1975-05-17 1976-11-22 Fujitsu Ltd Semiconductor unit manufacturing process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5191675A (en) * 1975-02-07 1976-08-11
JPS51126055A (en) * 1975-04-25 1976-11-02 Hitachi Ltd Contact part formation method in semi-conductor accumulation circuit
JPS51134566A (en) * 1975-05-17 1976-11-22 Fujitsu Ltd Semiconductor unit manufacturing process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739544A (en) * 1980-08-20 1982-03-04 Towa Seimitsu Kogyo Kk Arranging equipment of semiconductor frame
JPS6124818B2 (en) * 1980-08-20 1986-06-12 Michio Osada
JPS62154777A (en) * 1985-12-27 1987-07-09 Toshiba Corp Semiconductor device
JPS63131564A (en) * 1986-11-21 1988-06-03 Toshiba Corp Protective circuit for output

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