JPS58183537U

JPS58183537U - programmable equipment

Info

Publication number: JPS58183537U
Application number: JP7867082U
Authority: JP
Inventors: 尾形　好和; 酒井　芳克
Original assignee: 横河電機株式会社
Priority date: 1982-05-28
Filing date: 1982-05-28
Publication date: 1983-12-07

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の外観図、第２図は第１図実
施例のブロック線図、第３図は第１図実施例の要部構成
説明図、第４図、第５図は第１図、の動作説明図、第６
図は第３図の動作説明図である。１０・・・機器本体、１１・・・マイクロプロセッサ（
ＣＰＵ）、１２・・・システムＲＯＭ、ｌ　３・・・Ｉ
１０インタフェイス、１４・・・ユーザーＲＯＭ、　ｌ
　６・・−ＲＡＭ。２０・・・データバス、３０・・・プログラマ、３１・
・・プログラムＲＯＭ、３７・・・ＲＡＭ、３Ｂ・・・
演算ＲＯＭ。５０・・・コネクター、５１・・・雄コネクタ−，５２
・・・マイクロスイッチ、５３・・・雌コネクタ−，５
４・・・アクチュエータ。FIG. 1 is an external view of an embodiment of the present invention, FIG. 2 is a block diagram of the embodiment in FIG. 1, FIG. 3 is an explanatory diagram of the main part configuration of the embodiment in FIG. The diagrams are Fig. 1, an explanatory diagram of the operation, and Fig. 6.
The figure is an explanatory diagram of the operation of FIG. 3. 10...Device body, 11...Microprocessor (
CPU), 12... System ROM, l 3... I
10 interface, 14...user ROM, l
6...-RAM. 20...Data bus, 30...Programmer, 31.
...Program ROM, 37...RAM, 3B...
Arithmetic ROM. 50... Connector, 51... Male connector, 52
...Micro switch, 53...Female connector, 5
4...actuator.

Claims

[Scope of utility model registration request]

In a programmable device in which a user's ROM in which a user program is written using a programmer connected to a data bus through a male and female connector is mounted in a device body with a built-in CPU, a programmable device is provided on one of the male and female connectors. and a convex actuator provided on the other connector to operate the microswitch, and when the male and female connectors are connected or disconnected, the microswitch A programmable device, characterized in that the microswitch and the actuator are arranged so as to operate to put the CPU in a hold state and release the CPU from the hold state after electrical connection.