JPS58176928A - Light annealing - Google Patents

Light annealing

Info

Publication number
JPS58176928A
JPS58176928A JP5924782A JP5924782A JPS58176928A JP S58176928 A JPS58176928 A JP S58176928A JP 5924782 A JP5924782 A JP 5924782A JP 5924782 A JP5924782 A JP 5924782A JP S58176928 A JPS58176928 A JP S58176928A
Authority
JP
Japan
Prior art keywords
infrared
substrate
polycrystalline
processed substrate
flat plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5924782A
Other languages
Japanese (ja)
Other versions
JPH0351091B2 (en
Inventor
Junji Sakurai
桜井 潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5924782A priority Critical patent/JPS58176928A/en
Publication of JPS58176928A publication Critical patent/JPS58176928A/en
Publication of JPH0351091B2 publication Critical patent/JPH0351091B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation

Abstract

PURPOSE:To restrain deformation (warpage) of a processed substrate by a method wherein anneal processing is performed with flat plates made of light-permeable material being held into pressure contact with overall surfaces of the processed substrate. CONSTITUTION:A processed substrate 5 is held between flat plates transparent for infrared rays, e.g., quartz glass flat plates 6a, 6b with a thickness of approx. 5mm.. Pressing means 7 such as springs are used to cause these glass flat plates to come into pressure contact with the overall surfaces of the processed substrate 5 on both sides thereof. The processed substrate 5 is fixed through support means 8 onto a stage 4 in an anneal furnace of infrared radiation type such that the main plane (the plane having a polycrystalline Si layer formed thereon) of the substrate 5 is directed toward a first infrared lamp 1a having a function to focus an infrared ray. While moving the substrate at a given speed between both first and second infrared lamps 1a, 1b, it is scanned with an infrared beam to locally gradually melt the polycrystalline Si layer, so that the polycrystalline Si layer is single-crystalized by degrees.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は光輻射アニール炉を用いる光線アニール方法に
係シ、特に半導体基板等の平板状被処理基体に対する光
アニール方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a light beam annealing method using a light radiation annealing furnace, and more particularly to a light annealing method for a flat substrate to be processed such as a semiconductor substrate.

(b)  技術の背景 半導体装置の製造工程に於て、イオン注入領域の活性化
処理や多結晶シリフン層の単結晶化処理等の高温短時間
アニール処理成るいは局所アニール処理に際しり、赤外
線輻射加熱によるアニール方法が用いられる◎ (c)  従来技術と問題点 例えば5Oxs(s…con On Inmulat1
ng8ubstrat@ )の製造工程に於て、シリコ
ン(81)基板上に形成された絶縁膜上に能動素子の形
成基体となる単結晶81層を形成するに際して、前記絶
縁膜上に気相成長させた多結晶’81層を%鐘状の赤外
線ビームで走蒼し局所的KM次SSさせて行くことにょ
シ単結晶層化す□る方法が用いられる・又半導体装置に
於ける特定の機能領域を形成する際に1牛導体基板面に
選択的に不純物をイオン注入し、#半導体基板の表面部
を、11層1図にそあ水平断面を模式的に示したような
赤外線輻射アニール炉で例えば1000(”c)@ 1
o(秒)llfila短時間加熱して、前記イオン注入
領域を活性化するととKよシ、骸半導体基[K既に配設
されている他の機能領域に及ぼす影畳を少なく抑えて特
定の機能領域を形成する方法がある・なお111aii
lK於て1は棒状の赤外線ランプ、2は反射鏡、3は半
導体基板、Lは赤外−を示す。
(b) Background of the technology In the manufacturing process of semiconductor devices, infrared radiation is used during high-temperature short-time annealing or local annealing such as activation of ion implantation regions or single crystallization of polycrystalline silicon layers. An annealing method using heating is used◎ (c) Conventional technology and problems For example, 5Oxs (s...con On Inmulat1
In the manufacturing process of ng8ubstrat@), when forming a single crystal 81 layer that will serve as a base for forming active elements on an insulating film formed on a silicon (81) substrate, vapor phase growth was performed on the insulating film. A method is used in which the polycrystalline '81 layer is scanned with a bell-shaped infrared beam and localized to KM-order SS to form a single crystal layer.It is also used to form a specific functional area in a semiconductor device. During this process, impurity ions are selectively implanted into the surface of the conductor substrate, and the surface of the semiconductor substrate is heated for example at 1000 nm in an infrared radiant annealing furnace as shown schematically in the horizontal section of 11 layers in Figure 1. (”c) @ 1
When the ion-implanted region is activated by heating for a short period of time (seconds), the ion-implanted region can be heated to minimize the effect on other functional regions that have already been placed on the skeleton semiconductor substrate, thereby achieving a specific function. There is a method to form an area.111aii
In lK, 1 is a rod-shaped infrared lamp, 2 is a reflecting mirror, 3 is a semiconductor substrate, and L is infrared.

しかしこれら従来の方法に於ては、半導体装置のみがス
テージ上に平置されたシ、立てられた如し九状態で輻射
赤外線による加熱がなされていたので、半導体基板に、
後の製造工程に於て支障をきたすような(例えば密着露
光工程に於ける半導体基板の割れ、投影露光工程に於け
る焦点のぼけ等)大きな変形(そシ)が生じ、半導体装
置の製造歩留まりや性能が低下するという問題があった
However, in these conventional methods, only the semiconductor device was heated by radiant infrared rays while it was placed flat or upright on the stage.
Large deformations that may cause problems in subsequent manufacturing processes (for example, cracks in the semiconductor substrate during the contact exposure process, defocusing during the projection exposure process, etc.) occur, and the manufacturing yield of semiconductor devices decreases. There was a problem that performance deteriorated.

(d)  発明の目的 供し、上記問題点を除去することKある。(d) Purpose of the invention It is possible to provide a solution and eliminate the above problems.

(・)発明の構成 即ち本発明は、光騙射アニール炉を用いて平板状の被処
理基体に局所アニールを含む高温短時間アニール処理を
施す方法に於て、光線を透過する材質からなる平板を前
記処理基体の全面に圧接しながらアニール処理を行うこ
とを特徴とする〇(f)  発明の実施例 以下本発明を実施例について、図を用いて群細に説明す
る。
(・) Structure of the Invention That is, the present invention provides a method for applying high-temperature, short-time annealing treatment including local annealing to a flat substrate to be processed using a light beam annealing furnace. 〇(f) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings in terms of embodiments.

第2図は本発明の一実施91に於ける水平断面模式図(
イ)及びA−A’矢視垂直断面模式図(ロ)、第3図は
本発明の他の一実施例に於ける垂直断面模式図(イ)及
びA−A’矢視垂直断面模式図(ロ)である。
FIG. 2 is a schematic horizontal cross-sectional view of one embodiment 91 of the present invention (
A) and A-A' vertical cross-sectional schematic diagram (B), and FIG. 3 is a vertical cross-sectional schematic diagram (A) and A-A' vertical cross-sectional schematic diagram in another embodiment of the present invention. (b).

本発明の方法によシ、例えば前記80IS製造工程に於
ける多結晶81層の単結晶化を行うに際しては、!2図
0)及び(ロ)に示すように、被走査面に線状の焦点を
結ぶ赤外ML  を形成する機能を持つ第1の反射鏡2
aを具備した棒状のIllの赤外線ランプ1aと、被照
射面に対して垂直な平行赤外MLを形成する機能を持つ
IE20反射鏡2bを具備した棒状の第2の赤外線ラン
プ1bが対向して配設され、これら赤外線ランプの間に
左右方向に移動可能なステージ4が設けられた赤外線輻
射アニール炉が用いられる◎ 又80IS基敬を形成するための被処理基板としては、
例えば5〔吋〕径のSi基板表面に1〔μm〕程度の二
酸化シリコン(Slow)IIを熱酸化等の方法により
形成し、その上に気相成長方法によ〕例えば0.5〔μ
m〕程度の厚さの多結晶81層を形成し、更にその上に
厚さ0.5〜1〔μm〕程度のStow瞑戚るいは0.
1〜0.2〔μm〕程度の窒化シリコン(SisNa)
膜からなるカバー膜が形成されたものが用いられる・ そして本発明の方法に於ては、112図(イ)、(ロ)
K示すように1該被処理基板5を、赤外#!に対して透
明な平板1例えば5〔■〕程度の厚布の石英ガラス平板
6m、 6bによシ両面をら挾み、ばね等からなる加圧
手段7で該ガラス平板を被処理基、@5全面に圧接せし
めた状態で石英ガラス千[6a、6bで挾持する。そし
て前記赤外−輻射アニール炉に於けるステージ4上に1
、支持手段8を介して被処理基@5の主面(多結晶81
層が形成されている面)側を焦点を結ぶ機能を持つ第1
の赤外線ランプ1&負に向けて固定する。次いで被処理
基板5を、ステージ4と共Ks11!1、第2の赤外線
、ランプ11゜1b間を通して所定の速度で移動せしめ
る。このことによ!り、$I2の反射鏡2bを介して放
射される平行赤外MILKよシ被処理、基板すを約80
0 C℃)程度に予熱しつつ、その主面上を前記第1の
赤外線L′によって形成される線状の赤外線ビームによ
シ走査し、該多結晶St層を局所的に順次溶融させ、該
多結晶81層を順次単結晶化して行く。
For example, when monocrystallizing the polycrystalline 81 layer in the 80IS manufacturing process using the method of the present invention,! As shown in Figures 2) and (b), the first reflecting mirror 2 has the function of forming an infrared ML that focuses linearly on the surface to be scanned.
A rod-shaped Ill infrared lamp 1a equipped with a lamp and a rod-shaped second infrared lamp 1b equipped with an IE20 reflector 2b having a function of forming parallel infrared ML perpendicular to the irradiated surface face each other. An infrared radiant annealing furnace is used in which a stage 4 movable in the left and right direction is provided between these infrared lamps. Also, as a substrate to be processed for forming the 80IS base plate,
For example, silicon dioxide (Slow) II of about 1 [μm] is formed on the surface of a 5 [inch] diameter Si substrate by a method such as thermal oxidation, and then silicon dioxide (Slow) II, for example, 0.5 [μm] thick is formed on it by a vapor phase growth method.
A polycrystalline 81 layer with a thickness of about 0.5 to 1 [μm] is formed on top of the polycrystalline 81 layer with a thickness of about 0.5 to 1 [μm].
Silicon nitride (SisNa) of about 1 to 0.2 [μm]
In the method of the present invention, the method shown in FIGS. 112 (a) and (b) is used.
As shown in K, the substrate 5 to be processed is exposed to infrared #! A transparent flat plate 1, for example, a thick quartz glass plate 6m, 6b, with a thickness of about 5 [■] is held between both sides, and the glass flat plate is pressed against the substrate by a pressure means 7 made of a spring or the like. 5. Clamp with quartz glass sheets 6a and 6b while pressing the entire surface. 1 on stage 4 in the infrared-radiation annealing furnace.
, the main surface of the target group @ 5 (polycrystal 81
The first lens has the function of focusing on the surface (on which the layer is formed).
Infrared lamp 1 & fix it facing negative. Next, the substrate 5 to be processed, together with the stage 4, is moved at a predetermined speed between the Ks11!1, the second infrared rays, and the lamp 11.degree.1b. For this! The parallel infrared MILK radiated through the reflecting mirror 2b of $I2 reduces the substrate surface to about 80
While preheating the polycrystalline St layer to a temperature of about 0 C° Celsius, the main surface thereof is scanned by a linear infrared beam formed by the first infrared ray L′ to locally and sequentially melt the polycrystalline St layer, The 81 polycrystalline layers are sequentially turned into single crystals.

なお該多結晶S1層上に形成した前記カバーlI!は、
多結晶81層が溶融に際して石英ガラス平板61に付着
するのを防ぐためのものである0又本発明の方法により
、例えば前記イオン注入層の活性化を行うに際しては、
例えば第3図(イ)、(ロ)に示すような赤外線輻射ア
ニール炉を使用する0同図に於て、1は棒状赤外線ラン
プ、2は平行赤外線りを形成する機能を持つ反射鏡、4
はステージ、5は被処理基板、6は石英ガラス平板を示
している。
Note that the cover lI! formed on the polycrystalline S1 layer! teeth,
This is to prevent the polycrystalline 81 layer from adhering to the quartz glass flat plate 61 during melting. Also, when activating the ion-implanted layer, for example, by the method of the present invention,
For example, when using an infrared ray annealing furnace as shown in FIGS. 3(a) and 3(b), 1 is a rod-shaped infrared lamp, 2 is a reflector that has the function of forming parallel infrared rays, and 4
5 represents a stage, 5 represents a substrate to be processed, and 6 represents a quartz glass flat plate.

本発明の方法に於ては、同図に示すように、不純物のイ
オン注入領域が選択形成された例えば5〔吋〕径程度の
Si基板からなる被処理基板6を、その主面を上に向け
てステージ4上に平置搭載し、該主面上に、該主面全面
上を充分に被い且つ5〔■〕程度の厚さを有する石英ガ
ラス平板6を載置し、この状態でステージ4を所定の速
度で前記ア二一ル炉内を通過せしめることによシ、被逃
理基飯5の表面部を例えばi o o o (’c)・
10〔秒〕程度加熱し、前記イオン注入領域の活性化を
行う。
In the method of the present invention, as shown in the figure, a substrate 6 to be processed, which is made of a Si substrate having a diameter of about 5 inches, on which impurity ion implantation regions have been selectively formed, is placed with its main surface facing upward. A quartz glass flat plate 6 that fully covers the entire surface of the main surface and has a thickness of about 5 [■] is placed on the main surface, and in this state, By passing the stage 4 through the furnace at a predetermined speed, the surface portion of the escaping base material 5 is, for example, i o o o ('c).
The ion implantation region is activated by heating for about 10 seconds.

(2))−発明の効果 上記第1の実施例に於ては、被処理基板の局部加熱に際
して、被処理基@は両面から石英ガラス平版によって所
望の圧力で全面が挾みつけられた状態で加熱冷却がなさ
れる。従って、該赤外線アニール処理による被処理基板
の変形(そり)Fi大幅に減少し、例えば5〔吋〕シリ
コン基板に於て±0.5(#m)以下に抑えられる。
(2)) - Effects of the Invention In the first embodiment described above, when the substrate to be processed is locally heated, the substrate to be processed is sandwiched from both sides by the quartz glass plate with the entire surface under a desired pressure. Heating and cooling are performed. Therefore, the deformation (warpage) Fi of the substrate to be processed due to the infrared annealing treatment is significantly reduced, and can be suppressed to less than ±0.5 (#m) for a 5 [inch] silicon substrate, for example.

父上記第2の実施例に於ては、被処理基板全面の高温短
時間加熱に際して、被処理基板はその主面上に載置され
た石英ガラス平板の自重に二って全面が押えられた状態
で加熱冷却がまされる。従っそ該赤外線アニール処理に
於ても被処理基板の変形(そり)Fi第1の実施例同様
に減少し、例えt? 5 (吋)シリコン基1fIK於
て土0.5〔μm〕以下となる・ 以上説明したように、本発明によれば赤外線アニール処
理による被処理基板の変形(そシ)が極めて小さく抑え
られる0従って本発明は半導体装置特にSOI S構造
の半導体装置、イオン注入により機能領域を形成するこ
とが多い高集積度の半導体装置の製造歩留まり及び性能
を向上せしめるうえに有効である。
In the above-mentioned second embodiment, when the entire surface of the substrate to be processed was heated at a high temperature for a short time, the entire surface of the substrate to be processed was held down by the weight of the quartz glass flat plate placed on its main surface. Heating and cooling are done in this condition. Therefore, even in the infrared annealing process, the deformation (warpage) Fi of the substrate to be processed is reduced in the same way as in the first embodiment. 5 (x) The thickness of the silicon base is 0.5 [μm] or less in IK. As explained above, according to the present invention, the deformation of the substrate to be processed due to infrared annealing can be kept extremely small. Therefore, the present invention is effective in improving the manufacturing yield and performance of semiconductor devices, particularly SOIS structure semiconductor devices, and highly integrated semiconductor devices in which functional regions are often formed by ion implantation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1■は従来の赤外線輻射アニール炉の水平断面模式図
、第2図は本発明の一実施例に用いる赤外#Is射アニ
ール炉の水平断面模式図(イ)及びA −A′矢視垂直
断面模式図(ロ)、第3図は他の一実施例に用いる赤外
線輻射アニール炉の垂直断面模式図(イ)及びA−A’
矢視垂厘断面模式図(ロ)である。 図に於て% L 1mg lbは棒状の赤外線ラング、
L 2ae 2bFi反射鏡、3は半導体基板、4はス
テージ、5#−i被処理基板、6.6mg 6bは石英
ガラス飯、7#′i加圧手段、′8は支持子[9,Lは
被照射面に垂直な平行赤外線、L は普走査面に焦点を
結ぶ赤外線を示す〇 代理人 a埋土 松 岡 宏四a天n。
Fig. 1 is a schematic horizontal cross-sectional view of a conventional infrared radiant annealing furnace, and Fig. 2 is a schematic horizontal cross-sectional view of an infrared #Is radiant annealing furnace used in an embodiment of the present invention (A) and the A-A' arrow view. A vertical cross-sectional schematic diagram (b), FIG. 3 is a vertical cross-sectional schematic diagram (a) of an infrared radiation annealing furnace used in another embodiment, and A-A'
FIG. In the figure, %L 1mg lb is a rod-shaped infrared rung,
L 2ae 2bFi reflecting mirror, 3 is a semiconductor substrate, 4 is a stage, 5#-i substrate to be processed, 6.6mg 6b is a quartz glass plate, 7#'i pressurizing means, '8 is a supporter [9, L is Parallel infrared rays perpendicular to the irradiated surface, L indicates infrared rays focused on the normal scanning surface.

Claims (1)

【特許請求の範囲】[Claims] 光輻射アニール炉を用いて平板状の被処理基体に局所ア
ニールを含む高温短時間アニール処理を施すに際して、
光線を透過する材質からなる平板を前艷被処理基体の全
面に圧接しなからアニール処理を行うことを4I徽とす
る光アニール方法◎
When performing high-temperature, short-time annealing treatment including local annealing on a flat substrate to be treated using a light radiation annealing furnace,
A photo-annealing method in which a flat plate made of a material that transmits light is pressed onto the entire surface of the substrate to be treated before annealing is performed.
JP5924782A 1982-04-09 1982-04-09 Light annealing Granted JPS58176928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5924782A JPS58176928A (en) 1982-04-09 1982-04-09 Light annealing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5924782A JPS58176928A (en) 1982-04-09 1982-04-09 Light annealing

Publications (2)

Publication Number Publication Date
JPS58176928A true JPS58176928A (en) 1983-10-17
JPH0351091B2 JPH0351091B2 (en) 1991-08-05

Family

ID=13107857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5924782A Granted JPS58176928A (en) 1982-04-09 1982-04-09 Light annealing

Country Status (1)

Country Link
JP (1) JPS58176928A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144973A (en) * 1988-11-26 1990-06-04 Toko Inc Manufacture of thermal diffusion layer and manufacture of variable-capacity diode using the manufacturing method
US7410850B2 (en) 1997-03-11 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Heating treatment device, heating treatment method and fabrication method of semiconductor device
WO2009116763A1 (en) * 2008-03-17 2009-09-24 주식회사 티지솔라 Heat treatment method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144973A (en) * 1988-11-26 1990-06-04 Toko Inc Manufacture of thermal diffusion layer and manufacture of variable-capacity diode using the manufacturing method
US7410850B2 (en) 1997-03-11 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Heating treatment device, heating treatment method and fabrication method of semiconductor device
WO2009116763A1 (en) * 2008-03-17 2009-09-24 주식회사 티지솔라 Heat treatment method
JP2011515831A (en) * 2008-03-17 2011-05-19 ティージー ソーラー コーポレイション Heat treatment method
US8030225B2 (en) 2008-03-17 2011-10-04 Tg Solar Corporation Heat treatment method for preventing substrate deformation

Also Published As

Publication number Publication date
JPH0351091B2 (en) 1991-08-05

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