JPS58174985A - Logic circuit experimental apparatus for ic or the like - Google Patents
Logic circuit experimental apparatus for ic or the likeInfo
- Publication number
- JPS58174985A JPS58174985A JP5738882A JP5738882A JPS58174985A JP S58174985 A JPS58174985 A JP S58174985A JP 5738882 A JP5738882 A JP 5738882A JP 5738882 A JP5738882 A JP 5738882A JP S58174985 A JPS58174985 A JP S58174985A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- ics
- logic circuit
- experimental apparatus
- key
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Instructional Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、ＩＣ（集積回路）およびＬＩＣ、超ＬＳＩ等
の論理回路の実験をするための装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for testing logic circuits such as ICs (integrated circuits), LICs, and VLSIs.
従来のＩＣ等の実験ｒ（は、ｔヤッタリ／グ、雑音パル
ス、呼遊容瀘等の影＃をなくするため、ＩＣ川のフリン
ト基板上に回路を固定し、ハンダ付けを確実にして実験
をしなければならなかった。しか（７、学校等における
ＩＣの学習のだめには、学生ＶＣ多社類のＩＣを短時間
に習告させるため、一つ一つプリント基板を作成してハ
ンダ付けにより固定して実験することは極めて不便であ
る。Conventional IC experiments were carried out by fixing the circuit on an IC flint board and ensuring soldering in order to eliminate shadows such as yutter/g, noise pulses, and noise disturbances. However, (7) In order to have students learn about ICs from various VC companies in a short period of time, they had to make and solder each printed circuit board to finish their IC studies at school. It is extremely inconvenient to experiment with a fixed position.
本発明は、各種のＩＣが共通に使用可能なノケットを基
板上に固定しておき、また、論ＰＩＩ動作実験ＶＣ必装
なチャ、クリング防止用回路を備えたパルス人力″屯鋏
と、人力状態設定用電鍵と、クリヤおよびグリセット用
操作′亀鍵と、各ねの回路を構成するために必要とする
抵抗コンデンサ寺の回路素子を装着するための装置と、
人力出力状態の表示装置等を基板上に固定しておき、こ
の間の回路の設置こＶ（は、バナナフ゛ラクとバナナジ
ャックが一体と４・つタハ、チコード等を用いてＩＣノ
ケット等と連結したジャック間の接続を行なって、配線
を確実にして実験を行なうよう圧したＩＣ等の論理回路
実験装置を提供するものである。The present invention fixes a socket that can be commonly used by various ICs on the board, and also uses a pulse manual "tunscissor" equipped with a circuit for preventing cling, which is essential for PII operation experiment VC, and a human-powered An electric key for setting the status, an operation key for clearing and greasing, and a device for installing the circuit elements of the resistor capacitor required to configure each circuit.
The display device etc. of the human power output state is fixed on the board, and the circuit between them is installed. The purpose of the present invention is to provide an experimental device for logic circuits such as ICs, which allows connections between devices to be made to ensure wiring and conduct experiments.
本発明てより、短時間のうちに多くの種類のＩＣ等をさ
しかえて各種の論理回路の実験を行なうことができる。According to the present invention, it is possible to experiment with various logic circuits by replacing many types of ICs in a short time.
また、付属のシンクロスコープ、電圧計、電流計等をＩ
Ｃ等の外部から接続して、６易に電気的特性等の実験を
行なうことが可能である。In addition, the attached synchroscope, voltmeter, ammeter, etc.
It is possible to easily conduct experiments on electrical characteristics, etc. by connecting externally such as C.
以下本発明の詳細な説明する。The present invention will be explained in detail below.
本発明の実験装置に設置しである回路は、実験しようと
するＩＣ等に必要な付属の回路で、例えば、第１図のよ
うなＩＣへの入力パルスの整形とチャツタリング除去の
機能を有する単一パルス発生回路、第２図のクリヤとプ
リセットの回路、第３図の人力と出力の状態を表示する
表示装置の回路である。The circuit installed in the experimental apparatus of the present invention is an auxiliary circuit necessary for the IC, etc. to be tested. For example, the circuit shown in FIG. 2, a clear and preset circuit shown in FIG. 2, and a display device circuit that displays the state of human power and output shown in FIG.
第１図の回路□は、ＳＮ ７４０４またはＳＮ ７４０
０等のＩＣを用いて作ったフリップ・７０．プ回路であ
り、Ｇは接地、ＣＫは手動電鍵、Ｐｌ、Ｐ２は出力端子
で、ＣＫの切替毎にこの出力端子Ｐ１１Ｐ２かＬ〕チャ
ッタリ／グのない単一パルスがＩＣ等へ惧柘される。The circuit □ in Figure 1 is SN 7404 or SN 740
Flip made using 0 grade IC 70. G is the ground, CK is the manual key, Pl and P2 are the output terminals, and each time CK is switched, a single pulse without chatter/g is sent to the output terminals P11P2 or L] to the IC etc. .
第２図は実験しようとするＩＣ等のクリヤ（ＣＬＲ）や
、条件設定のだめのプリセット（ＰＲ）の操作用ＩＪＬ
鍵回路であり、ＰＵｌ、ＰＵ２は地気または電池を与え
クリアをする跳ね返り、ｋｉ、ｉｔｌ、ｐｓ、、 ｐｓ
２・・・・・ｉｔグリｔ！７ト用の電鍍である。Figure 2 shows the IJL for operating the clear (CLR) of the IC, etc. to be experimented with, and the preset (PR) for setting conditions.
It is a key circuit, and PUl and PU2 are bounces that give air or battery and clear, ki, itl, ps, ps
2... IT GRIIT! This is a 7-piece electric knife.
第３図はＩＣ等の入力・出力の倣少な変化を監視できる
ようにトランジスタ（Ｔｒ）で増幅して発光タイＡ−ド
（ＬＥＤ）および７セグメ／ト数字表小器（ＩＮＤ）Ｋ
よって表示するための回路である。Figure 3 shows a light-emitting tie (LED) and a 7-segment numeric table device (IND) that is amplified by a transistor (Tr) so that small changes in the input and output of ICs can be monitored.
Therefore, it is a circuit for display.
−Ｘらｐこ、この実験装置は、ＩＣ等の論理動作実験回
路を構成するために必要とする抵抗・コ／デ／リ−等の
回路素ｒ−を自由に装着できるようになっている。-Xrap This experimental equipment allows you to freely install circuit elements such as resistors, co/de/res, etc. required to configure logic operation experimental circuits such as ICs. .
（二の実験装置の実施例を第４図に、また外貌を第５図
に示す。第４図、第５図において、Ａ。(An example of the second experimental apparatus is shown in Fig. 4, and its external appearance is shown in Fig. 5. In Figs. 4 and 5, A.
Ｃ、ｆ、） 、 Ｅは１６ピ／のＩＣＣタケト、Ｂは２
２ビ／のＩＣＣチケットある。Ｊｌはこれらのノケ、ト
から１
取り出されたＩＣの端子に連結されたジャ、りを示す。C, f, ), E is 16 pin/ICC taketo, B is 2
I have an ICC ticket for 2B/. Jl indicates the jack connected to the terminal of the IC taken out from these holes.
ＳＷは人力情報を設定するスイッチで、スイッチの中点
に接続しであるＪ２ジャックを通して）各ＩＣの入力に
接続しＩＣへの入力条件（Ｈ又はＬ）を設定することが
できる。ＣＫは単一パルスを発生させる′電鍵で、Ｑ、
Ｑはこの出方用ンヤノクである。ＰＵはブ、７ユ式スイ
、チで、Ｉｃ素Ｆのクリヤ用パルスの出力に用いる。な
お、第１図の如き回路に限らず、クロックパルスを連続
的に発生させる整形機能付パルぞ発生回路を用いること
ができる。SW is a switch for setting manual information, and it is connected to the input of each IC (through the J2 jack connected to the middle point of the switch) and can set the input condition (H or L) to the IC. CK is an electric key that generates a single pulse, Q,
Q is the nyanoku for this way of coming out. PU is a 7-type switch and is used to output a clearing pulse for Ic element F. Note that the present invention is not limited to the circuit shown in FIG. 1, and a pulse generation circuit with a shaping function that continuously generates clock pulses may be used.
本実験装置を使って実験する場合には、各捗Ｉｃヲ１．
Ｃノケ、 ト（Ａ、Ｂ、Ｃ、Ｄ、Ｅ） Ｋ挿入シ、／ヤ
７りＪＩ、Ｊ２を用いて接続紐のついたプラグによって
配線を行ない、電ｗｃＫの操作にょシクロ、クパルス等
の人力を加える。またクリヤはスイッチＰＵで行ない、
出方はＬＥＤ（発光ダイオード）と７セダメ／ト数字表
示器で表示する。なお、付着のコノデノサ、抵抗等の配
線ＦｉＪ３のジャ、りを用いて適宜追加するようにする
。When conducting an experiment using this experimental device, each progress Icwo 1.
C, B, C, D, E (A, B, C, D, E) K Insert, /Y7 Use JI, J2 to wire with a plug with a connecting string, and operate the electric wcK. Add human power. Also, clearing is done with switch PU,
The direction of exit is indicated by an LED (light emitting diode) and a 7/7 numeric display. It should be noted that additional components such as attached connectors and resistors should be added as appropriate using the wires FiJ3.
以上は本装置ｄの便用の一例であるが、本装置を使用し
てこの他各稚の実験を簡単に行なうこ・とができる。The above is an example of the convenience of this apparatus d, but various other experiments can be easily performed using this apparatus.
ｌＸｘ図は本発明に用いるテヤッタリ／グ防止用回路の
１例を示す回路図、第２図は本発明に用いるクリヤ、プ
リセットの回路の１例を示す回路図、第３図は本発明に
用いるＬＥＤ等にょる出力表示装置の回路図、第４図、
第５図は本装置の一実施例を−示す配線図および外観図
である。
ＣＫ・・・クロ、クパルス人力用手動電鍵、ＰＬ、Ｐ２
・・・チャ、クリング防止用回路の出力端子、ＰＵ、Ｐ
Ｕｌ、ＰＵ２−り！Ｊ ヤ用電鍵、 ＰＳ、ＰＳＩ−
ＰＳ２・・・７’ ＋７セ、ト用電鍵、Ｔｒ・・・トラ
ンジスタ、ｌＪ：Ｄ・・・光Ａ、ダイオード、 ＩＮ
Ｄ・・・７セクメント数′ンｆｉ ｔｊ：：器、 Ａ
、Ｂ、Ｃ，Ｄ、Ｅ−ＩＣ７ケ、 ト、Ｊ、、 Ｊ２
・ンヤ、り、 ｓｗ・・・スイッチ、Ｑ、Ｑ・・・出
力用ジャック。
特許出願人 １１本′醒信電話公社
代 理 人 白 水 常 雄外１名
閉 １ 関
第 ２ 閃
培 ３ 関1Xx diagram is a circuit diagram showing an example of a leakage prevention circuit used in the present invention, FIG. 2 is a circuit diagram showing an example of a clear/preset circuit used in the present invention, and FIG. 3 is a circuit diagram showing an example of a clear/preset circuit used in the present invention. A circuit diagram of an output display device such as an LED, Fig. 4,
FIG. 5 is a wiring diagram and an external view showing one embodiment of the present device. CK...Black, Kupulus manual electric key, PL, P2
...Char, output terminal of cling prevention circuit, PU, P
Ul, PU2-ri! Telephone key for J Ya, PS, PSI-
PS2...7'+7', electric key for G, Tr...transistor, lJ:D...optical A, diode, IN
D...7 number of sectors'n fi tj:: vessel, A
, B, C, D, E-IC7 , G, J,, J2
・Nya, ri, sw...switch, Q, Q...output jack. Patent Applicant: 11 'Senshin Telephone Public Corporation Representative: Haku Mizu Tsuneo and 1 other person closed 1 Seki No. 2 Senpei 3 Seki
Claims (1)
機能を有する／ぐルス発生回路と、入力出力の状態を表
示する装置と、入力側の状態を設定するための電鍵と、
クリヤおよびプリセットの操作電鍵と、抵抗コンデンサ
等の回路素子を設定する装置 、および前記の各装置又
は回路の間を接続するだめの着脱自在の接続用具とが一
体化せる基板上に設置されたことを特徴とするＩＣ等の
論理回路実験装置。An IC socket device for inserting an IC, etc., a pulse generating circuit with a pulse shaping function, a device for displaying the input/output status, and a telephone key for setting the status of the input side.
A clear and preset operating key, a device for setting circuit elements such as a resistive capacitor, and a removable connection tool for connecting each of the above devices or circuits are installed on a board that can be integrated. An experimental device for logic circuits such as ICs, which is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5738882A JPS58174985A (en) | 1982-04-08 | 1982-04-08 | Logic circuit experimental apparatus for ic or the like |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5738882A JPS58174985A (en) | 1982-04-08 | 1982-04-08 | Logic circuit experimental apparatus for ic or the like |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58174985A true JPS58174985A (en) | 1983-10-14 |
| JPS617631B2 JPS617631B2 (en) | 1986-03-07 |
Family
ID=13054227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5738882A Granted JPS58174985A (en) | 1982-04-08 | 1982-04-08 | Logic circuit experimental apparatus for ic or the like |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58174985A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6111173U (en) * | 1984-06-26 | 1986-01-23 | 嘉穂無線株式会社 | IC circuit education board |
| JP2016051716A (en) * | 2014-08-28 | 2016-04-11 | 電子ブロック機器製造株式会社 | Electron block device |
-
1982
- 1982-04-08 JP JP5738882A patent/JPS58174985A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6111173U (en) * | 1984-06-26 | 1986-01-23 | 嘉穂無線株式会社 | IC circuit education board |
| JP2016051716A (en) * | 2014-08-28 | 2016-04-11 | 電子ブロック機器製造株式会社 | Electron block device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS617631B2 (en) | 1986-03-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lancaster et al. | CMOS cookbook | |
| KR970030552A (en) | Universal Burn-in Board | |
| JPS58174985A (en) | Logic circuit experimental apparatus for ic or the like | |
| MY122960A (en) | Method and apparatus for testing electronic devices | |
| US6895563B2 (en) | Universal laboratory prototyping interface system | |
| US3546793A (en) | Educational apparatus | |
| KR200295786Y1 (en) | electric block | |
| SG52753A1 (en) | Device for testing connections provided with pulling resistors | |
| KR101128400B1 (en) | Digital Electric Experiment Kit For Education | |
| KR200437346Y1 (en) | Bread-board for education | |
| US4074113A (en) | Punched-card programmable analog computer | |
| KR200266964Y1 (en) | Study Tools Using Digital Logic Gates | |
| KR200306981Y1 (en) | Logic Learning Tools Using Digital Logic Gates of Block Assembling Type | |
| CN216312235U (en) | Protection circuit and device applied to short circuit of connector | |
| KR200270732Y1 (en) | Electronic circuit study kit parts being eletrified by snap fastener adhesion | |
| KR200287163Y1 (en) | Digital electrical parts for electronic circuit study kit | |
| RU1789051C (en) | Radio-electronic kit | |
| US3792285A (en) | Electronic circuit installations | |
| KR200265631Y1 (en) | Digital electrical parts for electronic circuit study kit | |
| JPH03278085A (en) | Circuit learning device | |
| KR100418198B1 (en) | Digital electrical parts for electronic circuit study kit | |
| JPH07121104A (en) | Visual and real time logic circuit practice trainer displaying the input and output results of signal of screen of computer | |
| JP3135458U (en) | 3D encoder, 3D decoder, and simple decoder for teaching materials using a combination of 3D hexadecimal and binary numbers | |
| JPH0159550B2 (en) | ||
| JPH01187471A (en) | Random burn-in method |