JPS58168163A - Machine check processing system - Google Patents

Abstract

PURPOSE:To attain the processing efficiently at the generation of emergent machine-check interruption, by performing logical operation between machine- check interruption code correcting information and a machine-check interruption code, and forming a new machine-check interruption code. CONSTITUTION:When a service processor 3 patrols a central processing unit 1, and the stop of the unit 1 is detected, scanning log as to the unit 1 is collected and an error is analyzed. After the error analysis is completed, the service processor 3 produces a machine-check interruption code. The unit 1 performs logical operation between the machine-check interruption code information form the service processor 3 and the machine-check interruption code, and stores the result in a main storage device 2 as a new machine-check interruption code.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention dumps environmental status information into main memory when an emergency machine check occurs, and dumps environmental status information from a valid bit indicating the validity of error location information and environmental status information. In a computer system configured to store machine check interrupt codes consisting of
This relates to a machine check processing method in which EK is performed.

[Prior art and problems]

Figure N1 is a diagram showing an overview of the computer system to which the present invention is applied, and Figure 2 is a diagram showing the outline of the computer system to which the present invention is applied.
Figure 3 shows the configuration of the conventional Emergency! FIG. 2 is a diagram illustrating a thin check processing method.

In the figure, l indicates the central processing unit, 2 indicates the main memory, and 3 indicates the service processor. 0 If an emergency reporting error or serious error occurs in the central processing unit 1, the central processing unit fill Stop and service
Processor 3 processing time. Service Processor 3 scans out the status of Central, I & Salt Device 1
log and analyze the error details. The analyzed results are MC
ICE coded! 0 also reported during thin check interrupt. Environmental status information such as the contents of general-purpose registers, floating point registers, and control registers that have been operating up to that point are also stored in the main memory 2 at the time of machine check interrupt, and their validity is indicated by the valid bit of MCI C. ! At the time of syncheck interrupt, information such as KF;i, old PSW, new psw, contents of various registers, failing memory address, reeler 1 code, extended control code, MCIC, etc. is stored in main memory 2, and swapping of psw is performed. It will be done.

FIG. 2 shows the configuration of MCIC, and each bit has the following meaning.

SD2''V Indicates that a parity error in the microprogram address register or an error was detected in the system control routine.

PD: Indicates the occurrence of an error in the read/write command area or a retry failure.

SR: Indicates instruction buffer error, TLRPE% segment table origin error, successful recovery to KS8, and successful loading of service processor error.

TD: Indicates a 2-picture error at address 80, that is, an error has occurred in the interval timer.

CD: TOD Indicates that an error has occurred in the clock, CPU timer, or clock comparator. OED: Indicates that an error has occurred in the 0M mode or in the service processor. DG: Turns on when TL or B is urgent. Become.

W: Indicates power supply abnormality.

B: Unused D = Indicates that the interrupt mask is off and bending has occurred.

SE: Indicates that a 2-bit error has occurred in the main memory.

SC: Unused KE: Indicates that a 2-bit conflict error has occurred in key memory.

WP: Old PSWC) Indicates that the EMWP was stored correctly.MS: Indicates that the old PSW mask and key were stored correctly.

PM: Indicates that the program e-mask and condition code of the old PSW were stored correctly.

IA: Indicates that the old PSW instruction address was correctly stored.

FA: Indicates that the failing storage address was stored correctly.

RC: Service processor error Temporarily stored. (Model Depend) EC: Indicates that the ED code was stored correctly.

FP: Indicates that floating point registers were successfully logged out.

GR: Indicates that the general register has been successfully logged out.

CR: Indicates that the control register was successfully logged out.

LG: Unused ST: Turns on during recovery, indicating that the contents of the main memory are guaranteed.

C'l': Indicates that the CPU timer was correctly logged out.

CC: Indicates that the clock comparator was successfully logged out.

MCEL: All O's enter.

Note that the success or failure of reloading is notified by a league attack code together with an SR or ED machine check interrupt. If the league code is X 00000001' and ED is on, @ indicates that the service processor cannot continue processing, and the league code is X 0001.
0000' indicates an interrupt when loading is completed when SR is on.

In the conventional technology, the generation of MCIC is performed by the service processor 3 which has analytical capabilities such as scan out, and the dumping of various registers to the main storage 2 is also performed by the service processor 3.
This was done from processor 3. Further, the valid bit of the MCIC is also set to p by the service processor 3 when the dance of various registers is successful, and is stored in the main memory 2. FIG. 3 shows an outline of a conventional machine check processing method. The in-service processor 3 patrols the central processing unit 1, and when detecting a stoppage of the central processing unit 1, collects the scan log, performs error analysis, and generates MCIC. Then, the valid bit for the central processing unit 1 is turned on. Next, the central processing unit 1
The general-purpose register is read and the contents of the general-purpose register are logged out to the main memory 2. Log ara? MC if OK
Similar processing is performed for I, and MCIC is stored in main memory 2. After storing the MCIC in the main memory 2, the service processor 3 starts up the central processing unit. When activated, the central processing unit 1 swaps the PSW and executes the primary instruction. As shown in FIG.
It only monitors the central processing unit called patrol.

Direct zip processing is performed by the central processing unit 1. Therefore, the service processor 3 is generally implemented using low-speed, low-cost hardware. Therefore, the conventional method has the disadvantage that it takes time to perform register dumping, etc. [Object of the Invention] The present invention is intended to eliminate the above-mentioned disadvantage.

emergency! An object of the present invention is to provide a machine check processing method that enables dumping of various registers to main memory and storage of MCIC to main memory at high speed and efficiency when an interrupt occurs.

[Structure of the invention]

Therefore, the machine check processing method of the present invention is as follows:
In a computer system having a central processing unit, a main storage device, and a monitoring device that patrols the central processing unit, when the monitoring device detects a stoppage of the central processing unit, it monitors each part of the central processing unit. Performs a scan act, performs error analysis based on the scan-out result, creates a machine check m-in code according to the error analysis result, and indicates the contents of the various registers that should be logged out to the main memory whose contents cannot be guaranteed. The system is configured to create machine check interrupt code correction information and then start up the central processing unit, and the central processing unit:
When activated, the registers are logged out to the main memory, and the enable bit of the interrupt check interrupt code corresponding to the successful logout data is turned on.
A new machine check interrupt code is created by performing an arithmetic operation on the machine check interrupt code correction information and the machine check interrupt code, and then the new machine check interrupt code is stored in a predetermined location in the main memory. It is characterized in that it is configured to be stored in the storage area of .

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 4 shows an embodiment of the present invention.

The service processor 3 patrols the central processing unit 1 and detects that the central processing unit l has stopped.

Collect scan logs for the central processing unit 1 and perform error analysis. After performing error analysis, the service processor 3 generates the MCIC in advance. After generating the MCIC, the in-service processor 3 creates MCIC modification information. MCIC correction information is WP, M8 in Figure 2.
%PM, IA.

It has bits corresponding to FA%RC, EC, FP, GR., CR, LG, etc., and the effective bit position of registers whose contents cannot be guaranteed is set to logic "1". M.C.
After generating the IC modification information, the service processor 3
enables the central processing unit 1 and starts it. When the central processing unit l is started, it logs out general-purpose registers, floating point registers, control registers, etc. to the main memory 2, and registers the MCI for successfully logged out data.
Turn on the valid bit in C. Next, MCIC modification information and MCI C+2) AND-INVER8E theory mv
This is set as trMc I C and stored in a predetermined storage area of the main memory 2. By applying the AND-INVER8E logic, the valid bit of log data whose contents cannot be guaranteed is reset. After storing in MCI C1 in the additional memory area of main memory 2, central processing unit l stores P
Swap SW and execute the next instruction. Nae, AN
D-INVER8KIl*M (ANDi) is AAB→A.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, processing to be performed when an emergency machine check interrupt occurs can be performed efficiently and in a short time.

[Brief Description of the Drawings] Figure 1 is a diagram showing an overview of a computer system to which the present invention is applied, Figure 2 is a diagram showing the configuration of a machine check interrupt code (MCIC), and Figure 3 is a diagram showing a conventional computer system. FIG. 4, which is a diagram explaining the emergency machine check processing method, is a diagram showing an embodiment of the present invention. 1...Central processing unit, 2...Main storage device, 3 service processors. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] In a computer system having a central processing unit, a main memory, and a monitoring device that parses the central processing unit, the monitoring device detects a stoppage of the central processing unit. 1. Scan out each part of the above central processing unit, perform error analysis based on the scanning scan results, create a machine check interrupt code according to the error analysis results, and log-act to the main memory. is configured to create machine check interrupt code correction information indicating that the contents are not guaranteed among the types, and then start up the central processing unit, and when the central processing unit is started up, the above registers are logout to the above main memory, turn on the valid bit of the above machine check interrupt code corresponding to the successful logout data, and check the logic between the above machine check interrupt code modification information and the above machine check interrupt code. The apparatus is characterized in that it is configured to perform an operation to create a new machine check interrupt code, and then store the new machine check interrupt code in a predetermined storage area of the main memory. Machine check processing method 0