JPS58166734A - Analyzer for defectiveness in integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1990) The present invention provides an integrated circuit failure analysis apparatus KII having a means for matching the comparison levels of internal voltage images of an integrated circuit O.

(Background of the invention from z1) In the nearby city, the method of detecting the defective parts of the integrated circuit by observing the voltage tube inside the integrated circuit is now gone. The internal voltage can be obtained as a clear image (voltage image) by observing it with an integrated tube scanning electron microscope.

The false point 0 threat observation made by the above-mentioned method 11 is based on the image obtained from the standard integrated circuit and the image obtained from the integrated circuit under test.
However, since both circuits are of the same layer structure, the output of each scanning electron microscope is -ji! Dena-tame.

It has been expressed that there are inconveniences in making comparisons and judgments between these great players, and that they would like to see improvements made as soon as possible.

(3), Prior Art and Problems In a conventional O-scanning electron microscope, an energy analyzer is used to analyze the energy of secondary electrons from a semiconductor integrated circuit, which is an object to be viewed. A signal layer is provided in a secondary electron detection system for detecting secondary electrons.

However, the operating conditions for these devices have varied widely between lots of integrated circuits and materials! Due to factors such as i, the contrast levels of the voltage images O obtained by the secondary electron detection means may not necessarily match. Therefore, the voltage images to be compared are
'isg pressure o correct image thl isthmus and not :ap
, which causes problems in detecting and analyzing defective parts of these integrated circuits. Even if this defective pipe is adjusted manually, since the object to be inspected is an integrated circuit,
The amount of electron beam irradiation on the integrated circuit increases and this
The fact that it is destroyed can lead to further development, and it is urgent that this technique be improved.

(4). OBJECTS OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks of the conventional device O. Therefore, the 70th purpose is to compare the SIE image O of integrated circuits and to compare the comparative level of the two.
Set up quickly.

It is an object of the present invention to provide an integrated circuit failure analysis device capable of preventing damage to an integrated circuit caused by an electron beam.

The purpose of this invention is to irradiate a standard integrated circuit and an integrated circuit to be tested of the same type with a KIK beam, and to analyze the total energy of secondary electrons generated from each of the above circuits through a 4-ft. is detected by a secondary electron detection means to obtain a voltage image, and the voltage images are compared to detect a defective location in the above-mentioned integrated circuit;
In the failure analysis device for analysis, the secondary electron detection means is configured to be adjustable in gain, and
The energy analyzer f (D contrast maximizing analysis voltage) obtained in advance for each of the above circuits, the analysis voltage supply circuit that is applied without analyzing the energy during electron beam irradiation to each of the above circuits, and the secondary electron tenth circuit means for adjusting the gain of the secondary electron detection means in response to the output of the detection means to shift the output to a desired level range; This can be achieved by providing second circuit means for outputting an offset value to the level.

(6) 0-shot @D Example Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention, where 1 indicates an electron beam deflection coil of a scanning electron microscope (the entire structure thereof is not shown), and 2 and 3 respectively.

A standard integrated circuit and an integrated circuit to be tested (hereinafter, our circuits will be referred to as ICs) are subjected to an electronic beam 40 scanned by a deflection coil. These ICs were placed on an XY stage 5, and this xY stage was moved by a pulse motor 6, and the ICs placed on it were positioned at the appropriate position below the energy analyzer f71. It is configured to be scanned by the electron beam 4 described above later.

The standard integrated circuit 2 positioned at the appropriate position above is
1 and general test integrated circuit 3t IC2. ICI or IC2 (D
Positioning IaA pulse motor 6 [controlled by a control unit 0, for example, a computer 8].

The energy analyzer 4'7 is connected to an analysis voltage supply circuit 9, and under the control of this computer 8, contrast maximizing analysis voltages for ICI and IC2 (D) are preset by a conventionally known method. Find this OIE pressure k
In the circuit for supplying IcK, V, , V, resistor o
, switch 11. and digital-to-analog converter (
The output of the converter 12 is connected to the energy analyzer 7.

Reference numeral 13 denotes secondary electron detection means, which includes scintillators 14 and 7 that capture secondary electrons from the energy analyzer 7.
It consists of 15 otomaru. A circuit means #11 described below is connected to the gain control input of the photomulti 15. An analog adder 17, one input of which is connected to the output of the first (D circuit means 16 is the photomulti 15C); vessel 17f
iD output Ki1 connected analog digital converter (
DC) 1B, an arithmetic unit 20 to which the output of the converter 18 is connected via a switch 19. Arithmetic unit 20C) first output 2
Photomulti control register 2 set to 111H
2. and register 22t) from a digital-to-analog converter (DAC) 23 which converts the digital value to an analog value and provides this to the photomultiplier 150 gain control input.

Operation l12 (1) is connected from the second output 24 to the other input of the analog adder 170 via the switch 25';
A v-circuit means 26 is configured. The initial value of the offset value when the switch 2s is switched downward with respect to the drawing.

For example, -10 is supplied to the analog adder 17.

The switch 19 is connected to the random access memory (8M) 27 when switched to the lower side with respect to Figure IIi. There are two TVs at 28.29 in M27.

From operation s20, an end flag is generated at the end of the line scan, and the scan control circuit 36 responsive to this is issued to cause the scan control circuit 36 to start a frame scan session.

Also, the scan control circuit sOK is connected from the control s8 (line)
A line s1 that sends a scan start signal is connected. The circuit "300 output is connected to the electron beam deflection coil l.

The operating system of the device of the present invention having the above structure will be explained.

This invention O! Prior to entering the P-section operation, the switches 11, 19.degree. 25 under the control of the control section 8 are switched downward with respect to the drawing. Then, the scan start signal is 1i
i31 to the scan control circuit 30. When the electron beam deflection coil 1 is supplied to the scan control circuit 30, the V*child beam t" ICI
Under the control of the second section 8, the analysis voltage supply circuit 9tL is supplied to the energy analyzer 7 within a predetermined analysis voltage range, as shown in (2-1) in Figure 2, between 0 and 5. The applied analysis voltage was changed to 9\, and the secondary electron electron detection means 13. Analog adder 17DClg.

Then, the analysis voltage (2) which maximizes the contrast of the voltage gl (light/dark gII) stored in the RAM 27 and displayed on the teleset 28 is determined.

Subsequently, the XYXf-:154 moving sasser rIc2 is
- position in the program scanning area. Set it.

The contrast maximizing analysis voltage (■) is determined in the same manner as that for ICI K.

These voltages V, , V, are loaded into the register 10.

Then, the XY stage 5 is moved to move the ICI (2) into the electron beam scanning area again, and switch 1 is moved again.
1.19 to the upper side with respect to the drawing, t! 1111!
A line scan start signal is applied from 8 to the scan control circuit 30 to generate a scan tube for an appropriate number of lines of ICl0, and at the same time an initial tit value is set in the 7 otomaru control register 22. And energy analyzer 7
A contrast maximizing analysis voltage ■ is supplied to the resistor 1G from the resistor 1G. At this time, the secondary electron detection means 13 outputs, and the analog adder 17. MAX and MINt as shown in the lower line of FIG. 3 are determined from the signal values supplied to the arithmetic unit 20 via the system DC 18 and the switch 19. Using these values, the calculation section 20 performs all of the following calculations.

b = Vfnin aMIN + io ---
−−−−−−−−−−−−(2) However, formula (1), (2
), a ■ ma and ■ ml are voltage values obtained by the secondary electron detection means 13 and indicating the upper and lower limits 1 of a predetermined brightness modulation range on the voltage sound television 27Diii screen.

When these two values a and b are determined, under the control of the control unit 8, they are loaded into the a#:t photomulti control register 22, converted into analog values by the DAC 23, and then the photomultiplier 151D gain control ( Further, b is supplied to the other input of the analog calculator 17 through the switch 25t which is switched upward in the drawing, and is used for correcting the offset value.

After these operations are completed, an end flag is supplied from the arithmetic unit 20 to the scan control circuit 30 to cause ICI n-frame scanning.

ICIE obtained from frame scanning) @normal image F12
The next electron detection means 13 obtains the digital signal RA.
It is stored in M27.

Next, by moving the XY stage 5p, the IC2 is moved into the electron beam scanning area, and then the same processing as that applied to the ICI is performed to store the voltage image of the IC2 in the RAM 27 in a digital format. In this case, the OWX pressure to energy analyzer 1 #7 is ev as described above.

After that, each digital voltage signal stored in the RAM 27 is displayed as a bright and dark image on the television 28, 29, and the defective part of the IC 2, which is the object to be inspected, is found by comparing the images.

Perform analysis.

In this way, prior to finding and analyzing the IC2t) defective location, the photomultiplier 150 gain and the offset value given to the output signal of the photomultiplier 15 are automatically set, eliminating the need for manual frame adjustments as in the past. The problems caused by this can be removed. That is, defective location detection and analysis Kl! Cabinet meetings can be shortened, operability has improved, and I
This eliminates the risk of causing damage to the CI and causing the IC1 to become defective.

In the above embodiment, an example using televisions for ICI and ICZ was explained, but it is also possible to project two images on one television. It may also be used to determine whether the product is good or bad.

(7) Effects of the First Invention In short, according to the present invention, since the comparison voltage level between the standard integrated circuit and the integrated circuit to be tested is automatically corrected, defective locations can be detected.

Shorter analysis time, improved operability, ICI)
Prevention of damage, etc.tj! It can be done.

[Brief explanation of the drawing]

11th I! 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the generation of the contrast-maximizing analysis voltage.
Figure 0 is for the integrated circuit to be tested, and Figure 3 is a diagram illustrating calculation of the gain control value and offset value. In the figure, 2 is a standard integrated circuit, 3 is an integrated circuit to be tested,
7 is an energy analyzer, 13 is a secondary electron detection means,
9Fi analysis voltage supply circuit, 16 first circuit means, 26
Fi is the second circuit means. Patent Applicant Fujitsu Limited No. 2 (2-IJ (2-2) Figure 3 Temporary Opening Procedure Amendment (Jibbutton 1・Ifl'1. Reno (2) No. 2 1C Akira
(゛) Name () Hayabusa! I! Nishiki, mischievous tuna -----
---------3111i11 Column 4 Ruh ・Ii1'' (, Ninoseki f4#RyuγApplicant I1mi location 4-1015 Odanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture (522) Name Fujitsu Limited 4 Agent Address: 1015 Kami Elementary School 11J Naka, Nakahara-ku, Kawasaki City, Kamireigawa Prefecture, Fujitsu Ltd. " is corrected to "Energy Analyzer".

Claims (1)

[Claims] A standard integrated circuit and an integrated circuit to be inspected of the same type are irradiated with an electron beam 'fr, and the secondary electrons generated from each of the circuits are passed through an energy analyzer to detect secondary electrons. The voltage gIt- is obtained by detecting the voltage gIt-. In the failure analysis value of the integrated ifR circuit, which compares these voltage images to detect and analyze the defective parts of the above-mentioned integrated circuit to be inspected,
The secondary electron detection means is configured to be gain adjustable, and the contrast maximizing analysis voltage of the energy analyzer determined in advance for each of the circuits is set to 0.
@An analysis voltage supply circuit applied to the energy analyzer during beam irradiation, and the above-mentioned 2.
first circuit means for adjusting the second electron detection hand IRD gain;
2t) Circuit means 4 for responding to the small output of the secondary electron detection means R and fD and outputting a D offset value to a desired level of the output. Failure analysis of integrated circuits featuring -! IL