JPS58165375A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To enable a high speed operation, by forming word lines, power source lines, etc. of a good conductive material different from that of a wiring layer for gate electrode. CONSTITUTION:A static type memory is constituted of a semiconductor substrate 1, impurity diffused layers 2, isolation regions 3, etc. A poly Si wiring layer for word line WLP runs on the region 3. Wirings for gate electrode G3 and G4 of MOS transistors Q3 and Q4 which are cross-bound are formed of a conductive layer equal to that of the layer WLP via an insulation layer 4. The word line WL, a ground line GND, and the power source line Vcc are formed of a good conductive material such as molybdenum.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Issue-〇Technical Fees This invention relates to semiconductor memory devices, and more particularly to the structure of a static conductor memory device.

(Although the amount of 1iov is improving, the demand for i is still high.
0 (3) Conventional 1m technology and advantages Generally speaking, step-putter semiconductor memory devices are formed on a semiconductor substrate through a non-active layer, with nine word lines, bit line pairs,
With the power supply and ground wires connected, a nuta-titta type mesh cell is placed for the umbrella from each intersection KMO8>9V resistor with the PII pair on these O wires.

! Since then, the wiring for the gate electrode of the terminal is formed on the semiconductor with an insulating layer interposed therebetween. A conductive layer of 1II2, made of aluminum, for example, formed on the conductive layer with an insulating layer interposed therebetween. etc. so that it extends in a direction perpendicular to the direction in which word lines, etc. extend.
I was attacked. Therefore, for one memory cell,
In the row direction, a total of four polysilicon wirings run, including a word line, a wiring for the gate electrode of the cross-coupled transistor, and a pair of polysilicon wirings run in the column direction. A total of three aluminum wires were running: a bit line and a ground line. In one direction, the smaller the number of interconnections made of the same conductive layer, the easier it is to form interconnections, which improves yield and, in turn, improves the degree of integration. Also,
The higher the electrical conductivity of the word, bit line pairs, and power supply line materials, the faster access to memory cells can be expected. ... However, in the conventional $$, four polysilicon wires ran in the row direction and three aluminum wires ran in the 17" knee of the column, which made it easier to form interconnections, yield, In addition, the word lines and power lines are formed by polysilicon wiring for the gate electrode and the Oka-0 conductive layer, and resistance heavy lines (aluminum, etc.) are used. This was higher than that of materials with good conductivity, and prevented the access time from being increased.

(4) - In consideration of the above-mentioned conventional type, at least one of the word line, power line, and ground line is made of a conductive layer of a good conductive material different from the wiring layer for the dirt electrode. Based on the concept of creating a stacked structure, we have made it easier to form wiring layers in semiconductor memory devices manufactured by STATISTA to improve yields, which in turn improves the degree of integration and enables high-speed operation. (5) Invention In order to improve the above-mentioned 01 and 1a, the present invention is based on a word line formed on a semiconductor layer through an insulating layer, and a bit S □ electric Il! In a semiconductor memory device comprising a ground line and a ground line, and a MO8O8 transistor 14 static type memory cells arranged at each intersection of a word line and a pair of M'y lines, the dirt electrode of the mosquito MOIIF tunnel A conductive layer is formed on the conductor substrate with an insulating layer interposed therebetween, and at least one of the power supply line, the ground line and the word line is arranged on the conductive layer. The bit line is composed of a 30th conductive layer formed on the second conductive layer through the insulating layer, and the bit line is composed of a 30th conductive layer formed on the second conductive layer through the insulating layer. A semi, characterized by
~ (6) Embodiments of the Invention Hereinafter, embodiments of the present invention will be explained based on the drawings and compared with conventional examples.

Figure 1 shows a static type engine which is the object of the present invention.
2 is an equivalent schematic diagram showing one memory cell in a memory cell; FIG. In FIG. 1, there is an M08 transistor Q1 for memory 17. A word line WL is commonly connected to the gates of transistors Q, and a bit line BL is connected to the drains (or sources) of transistors such as i.

11 are connected to each other ◇MOS transistors Q H* Q that are cross-coupled to form a flip-flop
Drepun of 4 and source of Transimeta Q1sQ2 (
or drain) respectively at node N.

and -K or-. No') N,.

N1 is the load resistance blade 1. Via R2, Shi, Te'11
The source lines V,, K are connected and the sources are commonly connected to the ground SΦ.

-2nd garden is shown in 111- and is a nine-state ivy type map-le?
In the plan diagram showing the conventional structure of the semiconductor substrate 11280 to FIG. The impurity diffusion layer 2 is of type 1II.
(See Figures 3 and 41), semiconductor substrate 1
V-domain IIIWL and power supply line N1. . is running parallel to the line and direction. . Crossing, Minato Ai Mo1-
The wires G and G4 for electrodes are connected to the word @W'L and the power line v1. A conductive layer made of the same material as the K11III layer 4 on the semiconductor substrate is placed between the WL and VO in parallel to them (Fig. 2, Fig. 4). reference)
. Load resistance 1. R1 is polysilicon with a reduced amount of impurity ions, and a part of the diffusion layer 2 and the electric current mm
An insulating layer 4 is carved on a part of v through C. The dirt electrode G4, one end of the load resistor blade 10, and the diffusion layer 2 communicating with the drain region of the transistor Q3 are in contact jl*N.

I am in contact with. Dirt electrode arrangement I! lGs and load resistance l! One end of the diffusion layer 2 communicating with the drain region of the transistor Q4 is in contact with the load resistor B1. It is in contact with R2 (the other end of D is in contact with the power line V, .). WL.

G,, G4. R,,R,,V,a via the insulating layer 4, k' y) @BL,BL
It extends in the direction perpendicular to the extension direction, that is, in the column direction. BL, IL, and GND are formed by buttering the aluminum layer.
□,,・.

In contact with R4, a selection transistor Q is formed at the intersection of IL and WL, and a selection transistor Q is formed at the intersection of BL and WLjO, G,
and GNDO switching section, F transistor Ql is connected to G4 and GND.
Transistor Q4 is formed at the intersection with . Fujiri, B.
L and GND are covered with a phosphosilicate glass layer PIG.

As is clear from Fig. 42 and Fig. 4, in the conventional structure, one cell per cell is made of polysilicon in the row direction.
4 wires of I & Isaredaido-Wm, that is, W
L @ Gl'4 + vee exists, and three O distributions of nine conductive layers are carved in the column direction with an aluminum iJ-rim,
That is, BL, GND, and BL exist.

Next, 111g! The present invention will be explained in detail using diagrams from s to 7.

Figure 5 shows the static type memory cell t) shown in Figure 1.
*la@t) Plain WJl showing physical structure according to one embodiment
1%$14 FIG. 11I511D is a cross-sectional view taken along the line ■-Vl' 71Fi is a cross-sectional view taken along the line O■-■' in FIG. *S figure is small and happy 7 figure K or i, L1*2 and S are respectively □
, 11.・Conventional figure and vaso* Conductor substrate, impurity diffusion layer, and polys of word 411#1 on the 0 isolation region s which is the isolation region.
z9: In wiring layer WLP runs in the row direction.

The gate electrode wiring JIG and G4 of the cross-coupled MOS transistor Q and G4 are made of the same polysilicon as the conventional IIK polysilicon wiring layer WLP.
A conductive layer is formed on the medium conductive substrate 1 via an insulating layer F14. Load resistors R, , R, are made of polysilicon doped with a reduced amount of impurity ions and are formed on a portion of the diffusion layer 2 with an insulating layer 4 interposed therebetween. There is no conventional power supply line made of polysilicon. WLP,
Gs, G4. A word @WL, a ground line GND, and a power line V are connected on R,,R, through an insulating layer 4t. but,
It is formed parallel to Gs and G4. Word sWL is in contact with polysilicon wiring layer WLP. WL, GN
D and Chi. is composed of a #I2 conductive layer using a highly conductive material such as molybdenum, tungsten, or aluminum. Through the insulating layer 4 on WL, GND and vo,
Bit line pairs BL and n are formed extending in direction 1, that is, in the column direction, perpendicular to the direction in which WL and the like extend.

Bit line pairs BL and BL are also constructed of a fifth conductive layer made of a highly conductive material such as aluminum, as in the conventional case. BL.

BL is covered with PSG as before. Contact) MI
IIN,~''N2 is provided with subordinate Qin open mK・wi2
Figure 0
O wiring Bl,, GND, Bl, exist -I
IX% In this embodiment, the bit line pair BL and BLO2 are injured in the row O. This ninth column direction O wiring distance is larger than the conventional example if the dimensions of the two rows are the same. ζOhi means that the formation of II*O is equal to 1 compared to the conventional method, and therefore, according to this embodiment, the 1111-reduction is improved. Furthermore, in this embodiment, column direction vI! If the line-to-line spacing is made equal to that of the conventional example, the gap between the bit holes will be approximately R17 compared to the conventional example, and the degree of integration will be greatly improved.

In order to focus on the large row direction, and in the conventional example, polysilicon 0I
ll), is O which is made as a mask when forming the impurity diffusion layer 2, and 9 is (lI
Ren, see Figure 4), in the non-example, after carving the diffusion layer 2, the conductive layer of fluorium, etc. is formed with the conductive layer of II2, so one part of the diffusion layer 2 is Electric +1 to cover the area
1i line v0 can be formed. For this reason, 1
As shown in Figure 115 and Figure 7, itg*v
A power source SV- is formed such that two parts of the diffusion layer 2 and a part of the diffusion layer 2 overlap. Depending on the ζO configuration, the word line WL and the power line V. The interval tll between the gates is shorter than that of the conventional example, which improves the degree of integration.

Further, the word l1WL was conventionally formed of polysilicon, but in this embodiment it is formed of a highly conductive material such as aluminum, so that the word line WLK is
The R time constant is smaller than in the past, allowing high-speed operation.

In addition, in the above-mentioned example, ``word wrap WL, ground -〇ND
, and '11111 [V t't-, the 9 formed by the 20th conductive layer is at least one of WL, GND, 9''
Form the book with the second conductive layer, and remove the remaining wiring.
1"t'nio, 工, t;ya, □...

be caught.

(7) Effects of '4' As mentioned above, according to the present invention, word lines, power lines, and ground lines Oat< and %1 can be formed using a conductive layer made of a highly conductive material similar to a wiring layer for a gate electrode. By forming the layered structure, it becomes easy to form the wiring layer O of the static semiconductor memory device. It is expected that the yield rate will be improved, the degree of integration will be greatly improved, and high-speed operation will be possible.

[Brief explanation of the drawing]

Static type Tsun f which is the counter voltage of 111iti Honfumei
Equivalent circuit diagram showing Muatasemme 4S01 memory 7rukai, 1
A plan view showing the conventional 011 objective structure iIk of the metallic type memory cell of I211tt 11i11, FIG.
Figure 2 Ol-1' line break-■, l! Figure 14 shows ■-W in Figure 2.
'Line section-diagram, states k shown in diagram 1 (
) Figure 4 of Hei-1-1 showing the physical structure according to one embodiment of the invention is M-Vl' in Figure 5.
It is a sectional view taken along the line ■-■' of FIG. 5. -″′:′- 1.-semiconductor substrate, 2-.impurity diffusion layer, t.-region, 4.-insulating layer, WL..-word line, BL, BL
...Beep) pair, ■ ...Power wire, GND...
・Grounding wire, Co1eG4...Wiring for gate electrode. Patent applicant Fujitsu Ltd. Patent application fee J! Patent Attorneys: Akira Aoki, Patent Attorneys: Kazuyuki Nishi and Kazuyuki Tate 1) Yukio, Patent Attorney, Yoshiyuki Yamaguchi 1st session Figure 2 Figure 3 11,',' Figure 4 Figure 6 Procedure amendment Written by: Yuzuki 1, 1980 Kazuo Wakasugi, Commissioner of the Japan Patent Office 1. Indication of the case 1982 Patent Consultant No. 32233 2. Name of the invention Semiconductor storage device 3. Person making the amendment Relationship to the case Name of the patent applicant ( 522) Fujitsu Ltd. 4. Agent (external 3. 5. Subject of amendment (11) Column for detailed explanation of the invention in the specification (2) Drawings (Fig. 7) 6. Contents of amendment (1) Description "l" on page 10, line 7 and line 12 of
is corrected to "11". (2) Amend the attached drawing Figure 7 as per Attachment M, 7. Inventory of Source Documents Revised Drawing C Figure 7) 1 copy □

Claims (1)

[Claims] 1. A word formed on a semiconductor substrate via an insulating layer.
, p) A semiconductor i which is equipped with a one-to-two electric one-to-one and one-to-one ground #11 meeting, and a static type memory 7 which can also be a transistor is arranged at each intersection of a word line and the beat line pair. In the device, the wiring for the gate electrode of the MO1l) transistor is formed by a conductive layer on the semiconductor substrate via the insulating layer.
Ground line j and ii word line O゛at least one -1'
〇-Electric layer... -□ Formed through an insulating layer and composed of two conductive layers, 〇゜) $1 is applied to the second conductive layer, then the second conductive layer, then the second conductive layer, Intermediate...1
1. A semiconductor memory device characterized in that the semiconductor memory device comprises a conductive layer having a conductive layer of about 69 m. '2, Mukuro No. Lead 1111a#'l12om one layer. i,-
1 (Yo is 111:11) Arranged so that it extends in the direction perpendicular to the 9th direction.
′・□゛, 1・j The semiconductor device according to claim 1111 characterized by