JPS58164342A - Simultaneous transmission system for plural data - Google Patents

Abstract

PURPOSE:To transmit simultaneously plural serial data which differ in pulse width through one transmission line and to regenerate respective data signals separately on a reception side. CONSTITUTION:At a transmission side, two serial data signals D1 and D2 are inputted to an EXOR1 and data signals D3 and D4 are inputted to an EXOR1'; and their output signals (a) and (b) are inputted to an EXOR1'', which transmits one composite data signal. On the reception side, the composite data signal is integrated by plural integrating circuits 2-5 and branched to four branching circuits. The integrating circuit 2 has the greatest time constant and the integral output signal of the received input signal is shaped by a buffer amplifier 6 with a specific threshold value to obtain the regenerated data D1' of the data signal D1. In the same way, the time constant of the integrating circuit 3 corresponds to the data signal D2 and on the basis of the output signal of the integrating circuit 3, a data signal D2' corresponding to the data signal D2 is obtained. Similarly, correspoinding data signals are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system for transmitting and receiving a plurality of data through a single transmission path.

In order to multiplex transmit a plurality of data per signal, the signal is converted into a multiplexed signal using the F8 method in the PCM method, and then sent and received. These devices can arbitrarily multiplex a large number of data signals at a data rate within a predetermined band, and have a high degree of freedom as there are no data types. However, even if the amount of data to be transmitted is small and the liquid form of the transmitted data and the reproduced data on the receiving side allow some error in the pulse width part, the specified conversion device and transmission The rounding circuit required is large in size and expensive, and has a disadvantage.

An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a multiple data simultaneous transmission system that can transmit multiple pieces of data each having a different pulse width using a simple configuration and an inexpensive circuit. be.

The transmission system of the present invention includes at least one exclusive OR circuit that inputs two serial data signals with different pulse widths and outputs the exclusive OR of the input signals, and N serial data signals with different pulse widths. A transmitting circuit that exclusive ORs data and outputs it as one composite data signal, and a receiving side,
An input section that branches a received input signal into N branch circuits by connecting at least N -1 integrator circuits with different time constants in parallel; and an input section that shapes and outputs the signals of each branch circuit output from the input section. a first monostable multivibrator triggered by the rising edge of the output signal of the buffer amplifier and a second monostable multivibrator triggered by the falling edge of the output signal of the same buffer amplifier. A multivibrator and an N-1 (N-1) (pulse width identification circuit) consisting of an AND circuit that outputs the logical product of the first and second monostable multivibrators,
- one data signal is reproduced and outputted from each of the N-1 pulse width discrimination circuits, and a data signal with a maximum pulse width is connected to the integration circuit having the maximum time constant and reproduced and outputted from the nine buffer amplifiers; It is characterized by

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

That is, on the transmitting side, the two serial data signals 1 and 8 are input to the exclusive OR circuit 1, the data signal 8 is input to the exclusive OR circuit 1', and the above two exclusive OR circuits are input. 1. ,．． The output signals a and b of 1' are input to the exclusive OR circuit 1', and the exclusive OR circuit f also transmits the exclusive OR of the four data as one composite data signal C. By combining the exclusive OR circuits in this way, the exclusive OR of the data of NIm can be transmitted as one composite data. Although the above N pieces of data are expressed on pulses having different pulse widths, the symbol intervals may be the same or different. Of course, the N pieces of data do not need to be synchronized with each other.

If there are two pieces of data to be transmitted, it goes without saying that only the exclusive-rational sum circuit 1 is sufficient. Now, when the data signals ~D4 have the waveforms shown in Figure 2 (to) ~I, respectively,
Output signals a and b of Kosen's striped circuits 1 and 1'
have the waveforms shown in Figure 2 (g) and ψ), respectively. The composite data signal C output from the exclusive filling circuit r is as shown in FIG. That is, the composite data signal C is
'', and an even number of input pulses causes "◇". However, since the pulse width of each data signal is different, the rising edge and falling edge of each data signal are always the same as the composite data signal e.
The composite data signal C, which corresponds to either a rising edge or a falling edge, is transmitted to the receiving side via a transmission path. The received input signal d is substantially the same as the signal C described above.

On the receiving side, the input signal d is passed through a plurality of integrating circuits 2 to 2.
5 and branches into four branch circuits. The integrator circuit 2 is an integrator circuit with the largest time constant, and the output signal obtained by integrating the received input signal d is shaped as shown in FIG. If so, it is possible to output a reproduced data signal A' into a data signal as shown in FIG. On the other hand, the time constant of the integration circuit 3 corresponds to the pulse width of the data signal (data signal with a narrow pulse width), and the response to the pulse of D4 is small. Therefore, the output signal f of the integration circuit 3 is As shown in Figure 3 @), if this is shaped by the buffer amplifier 7, it becomes a signal g as shown in Figure n.

The signal g has almost the same waveform as the signal a shown in FIG. triggers the third monostable multivibrator 11. The first and second monostable multivibrators 1G and 11 output pulses with a narrow constant time width (the pulse width of the triggered data is also wider than the pulse width of the data); During output, it is not retriggered, so the output signal of the first monostable multivibrator 10 has a waveform as shown in FIG. The waveform will be as shown in (g). Both signals above.

1 is input to the AND circuit 12, and the output of the AND circuit 12 produces a data signal D! as shown in FIG. It is possible to obtain the reproduced data signal ′. The monostable multivibrator 10.11 and the AND circuit 12 constitute a pulse width discrimination circuit.

Next, the integrating circuit 4 has a time constant corresponding to the pulse width of the data signal D4, and its response to the pulse of the data signal D4 is small. Therefore, the output signal j of the integrating circuit 4 is
As shown in the picture. When the signal j is shaped by the buffer amplifier 8, the output signal becomes as shown in FIG. 6 (6). The signal includes a data signal D+ "" Da
, but does not have a component of data signal D4. A rising edge of the signal triggers the monostable multivibrator 13, and a falling edge of the signal triggers the monostable multivibrator 14. Monostable! Multipibrator 13,1
The width line of the output pulse No. 4 is set to be medium thicker than the pulse width of the data signal D1, and narrower than the pulse width of the data signal DIO. Therefore monostable multivibrator 18.14
0 output signal 1. m becomes waves as shown in W, 4, 0 and OK, respectively. The signal 1. If m is input to an AND circuit 1sK and a logical product is performed, the components of the data signal -1) Dm and ri are removed, and only the components to the data signal are reproduced as shown in (I)K in the same figure. A data signal DI is obtained. The monostable multivibrators 13 and 14 and the AND circuit 151 constitute a pulse width discrimination circuit.

Furthermore, the integration circuit 5 has a small maximum time constant, and because most of the reception input (1!4) is passed through and input to the Patzer-A-P 9, the high-frequency noise that is encountered with the reception input signal is small. In this embodiment, the integral circuit !S may be omitted and input directly to the par 7 amplifier.
3.4 and the above integral circuit S (may be omitted)
This constitutes an input section that divides the input signal into four branch circuits.

Generally, the input part that branches to the branch circuit of Numl is N-1
It can be constructed by connecting several integrating circuits in parallel. However, in order to remove high frequency noise, it is desirable to use N integrating circuits. The output signal n of the integrating circuit 5 is
The waveform is shown in FIG. 4 (G). The signal n includes all pulse components of the data signal -D. The signal O obtained by shaping the signal n by the buffer amplifier 9 is the fourth
The result will be as shown in the figure. By triggering the monostable multivibrators 16 and 17, which output pulses with a width slightly wider than the pulse width of the data signal D4 and narrower than the pulse width of the data signal Da, at the rise and fall of the signal 0, the monostable multivibrator is activated. 16, 17 output signal p.

q is the function of Figure 4, and K as shown in @. If the above signals p and q are input to the AND circuit 18, the AND circuit 1
The reproduced data signal Dj of the data signal D4 as shown in FIG. 4 (,T) can be obtained by the output signal of 8.

The monostable multivibrator 16.degree. 17 and the AND circuit 18 constitute one pulse width discrimination circuit. Although three such pulse width discrimination circuits are provided in this embodiment, for general KN data signals, N-1 pulse width discrimination circuits are provided. Then, by shaping the output of the integrating circuit with the maximum time constant for the data signal with the maximum pulse width, a 1% raw data signal is obtained,
For the remaining DON-1 data signals, N-
111O It is difficult to obtain a reproduced data signal using the pulse width discrimination circuit. The above circuit is simple), PCM
This has the advantage that multiple O data can be transmitted without using a large-scale multiplexing device of the conversion device.

As mentioned above, in this real @, the NfaO data are Nll serial data signals with different pulse widths,
The exclusive OR of N*0 data signals is taken and sent as one multitone data signal, and on the receiving side, at least N-1 integrator circuits with different numbers of pulses are used to convert x@O min@shunt circuit. The output signal of the integral circuit O with the maximum time constant is shaped to reproduce the maximum pulse width O data compensation, and the remaining j) ON
- One O branch circuit is used to shape the output signal of the integration circuit (one can be omitted), and the first and second monostable circuits are formed according to the rising and falling edges of the good signal. By triggering the multi-pipe rake and combining the outputs of both of the multivibrators with an AND circuit, the corresponding N-1 data signals are separated and outputted by a separate circuit for each pulse. Multiple direct data with different widths can be easily configured using a single transmission line OR circuit, integration circuit, monostable multi-by-play, AND circuit, etc., and it is not possible to use large-scale data as in conventional multiplex transmission systems. This has the advantage that a relatively small amount of data can be simultaneously transmitted through one transmission path without using a conversion device or the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including a partial logic circuit diagram showing one embodiment of the present invention, and FIG. 2 is a time chart showing signals of each part of the transmitting circuit of the above embodiment.
12 is a time chart showing notes of each part on the receiving side of . In the figure, 1.1', 1#...exclusive OR circuit, snow~S--integrator circuit, -~9...buffer amplifier, 1G, 18.16-...first monostable multi Vibrator, 11, 14, 17...Second monostable multi-vibrator-112, 15, 18...AND circuit. Agent Patent Attorney 1) Toshi Sou

Claims (1)

[Claims] At least one exclusive OR circuit that inputs two serial data signals with different pulse widths and outputs the exclusive OR of the input signals, and performs exclusive OR of N pieces of data each having different pulse widths. A transmitting circuit that outputs one composite data signal, and an input that branches the received input signal into N branch circuits by connecting in parallel at least N-1 integrating circuits with different time constants on the receiving side. a first monostable multivibrator that is triggered by the rising edge of the output signal of the buffer amplifier, and the same buffer amplifier. A second monostable multivibrator that is triggered by the falling edge of the output signal of 4, and an AND circuit that outputs the logical product of the first and second monostable multivibrators, each having an N-1 pulse width. 0N-1 data signals other than the large pulse width are reproduced and output from the N-1 pulse width identification circuits, and the data signal with the maximum A# width has the maximum time constant. A simultaneous transmission system for a plurality of data, characterized in that the buffer amplifier connected to the integrating circuit reproduces and outputs the data.