JPS58162110A - Current source - Google Patents

Abstract

PURPOSE:To compensate the influence of a channel length modulating effect, and to have high output resistance, by providing an MOST whose source and gate are connected to an input and an output of an inverting and amplifying circuit, and an MOST connected between said source and a DC power source. CONSTITUTION:An input of an inverting and amplifying circuit constituted of an MOS transistor (TR) 11 and 12, and its output are connected to the source of the first MOSTR 13, and its gate, respectively, and also to the source of the MOSTR 13, the second loading MOSTR 14 is connected. Also, the drain of the MOSTR 13 is used as an output terminal 30 of a current source. When the potential of the output terminal 30 rises by a load variation, a drain current of the MOSTR 13 is inclined to increase by a channel length modulating effect, but since an increase of the current is generated in the MOSTR 14, too, in the same way, a voltage drop increases, and the potential fo a node 21 rises. This potential rise is inverted and amplified by an inverting and amplifying circuit, and is sent to the gate of the MOSTR 13 as a potential drop of a node 22, so that an output current does not increase.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on MO
This relates to a current source for an S transistor.

FIG. 1 shows a typical example of a conventionally used MOS transistor current source (hereinafter simply referred to as a current source).

In the figure, 1, 2 and 3 indicate MOS transistors (hereinafter referred to as MθST), and in this example, 1 is a depletion type NUST (hereinafter referred to as D-NO8T), 2
．． 3. Enhancement type MO8T (hereinafter E-MO8T)
) are used respectively.

In this example, each MO8T is a H-channel type device, and 10 in the figure indicates a high-level side power supply voltage terminal, 20 indicates a low-level side power supply voltage terminal, and 30 indicates an output terminal of the core power supply.

In the circuit shown in Figure 1, D-M (JSTI and E-M (JSTI)
8T2 is connected in cascade between power supplies 10 and 20 to form a bias circuit, and the voltage generated at node 4 is connected to E-M.
Lead to the gate of O8T3. E, the source of MO8T3 is connected to the power supply 20, and the drain is connected to the output terminal 3 of the current source.
It becomes 0. Now, E-NU8T2 and 3 are composed of transistors of the same size, and E-M (JST3
Assuming that the output resistance of is sufficiently large, E-1! JU8T
Since the gate-source voltages VG8 of 2 and 3 are equal, E-
Regardless of the voltage at the output terminal 30, a current approximately equal to the current flowing through MOFTI and MOFT2 of the bias circuit always flows into MUST3, so that a constant current source can be configured.

By the way, the most important requirement for a current source is that the current of the current source does not change due to a change in the voltage at the output terminal, that is, that the output resistance is high.

- For example, the common mode discrimination ratio of a differential amplifier circuit is directly proportional to the output resistance of the current source used in the circuit. However, the current-voltage characteristic of E-IVIO8T3 in FIG. 1 has a finite slope, ie, output resistance r, as shown in the M2 diagram. It is known to have

This phenomenon is called the channel length modulation effect, and is called the channel length modulation effect.
, the output resistance tends to decrease more and more as the channel length of MO8T3 decreases. Therefore, the current source configured as described above has the disadvantage that the output resistance decreases and a stable current source cannot be obtained.

It is an object of the invention to provide a current source which compensates for the reduction in output resistance due to the influence of the channel length modulation effect and has an apparently high output resistance.

The current of the present invention is connected to an inverting amplifier circuit, a first ON (JS transistor) whose gate is connected to the output of the inverting amplifier circuit, and whose source is led to the input of the inverting amplifier circuit;
The second load M(JS) transistor is connected between the source of the M(JS) transistor and the DC power supply, and the drain of the first MOS transistor is used as the output terminal.

Embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a circuit diagram of an embodiment of the present invention.

In the figure, 11, 12, 13, and 14 are respectively smoke O8T.
In this example, 11 is p-Mo5T, 12
, 13.14 and E-440S'I' are used, respectively. Further, in the figure, 10, 20, and 30 are the same components as in FIG. It should be noted that this embodiment will also be described on the assumption that each MO8T has an N-channel type polarity, as in the case of FIG. 1. Therefore, power supply voltage supply terminal 1
The polarity of the voltage supplied to 0.20 and the polarity of the current flowing through the output terminal 30 of the current source will be the same as in FIG.

In this embodiment, MO8TII and N08T12 are connected in series between power supply terminals 10 and 20, and D-MO
An inverting amplifier circuit (inverter circuit) with an E/D configuration is configured, with 8TII as a load and E-MO8T12 as a driver. The input of this inverter circuit, that is, E-fV
The gate of IO8T12 is connected to the source of the first MUST13, and the output, ie, the drain of E-uos'r12, is connected to the gate of the first MUST13. Furthermore, the source of the first MO8T13 has a second E-IVI for load (JST14
The source of the second E-flJ (JST14) is connected to the low-level power supply terminal 20.The drain of the first IVIO8T13 is connected to the output terminal 30 of the current source.

Next, the circuit operation of this embodiment will be explained. First, assuming that the potential of the output terminal 30 increases due to load fluctuation, the drain current 113 of M Since this also occurs at MU8T14, the voltage drop at IVIUST14 increases, and the potential at the source of node 21, ie NO, 9T13, increases.

5- The potential rise of this node 21 is MO8Tll and MO8'l
MO8 is inverted and amplified by an inverter consisting of MO8.
Sent to gate T13. This result IVIO8T13
Since the gate-source voltage VG8 of M(JS
The current I11 of T13, that is, the output current of the current source, hardly increases, and a near-ideal constant current characteristic in which the channel length modulation effect is compensated for is obtained. The operation of this embodiment has been described above in the case where the potential of the output terminal 30 increases due to load fluctuations, but as explained above, the operation is completely opposite to that described above when the potential of the output terminal 30 decreases. It should be obvious. In order to further clarify the effect of this example, the mutual conductance and output resistance of M (JST13) are 9m13 and r13, respectively,
The equivalent resistance of 14 is r14, and the amplification degree of the inverter circuit is -
As A, the output resistance rQ of the current source is written as rOo r sa+r 14+grn 13(1+A)
rxs rn. In the above formula, gmta r13 is 1
Since the general value is 0 or more and A is 10 to 100, the output resistance r0 of the current source in this example is MO8T13
The output resistance r, 3, obtained when R is used alone is dramatically increased.

As described above, according to this embodiment, the increase in output current caused by the channel length modulation effect is extracted as a voltage drop at the load M (JST14), and this is negatively fed back to the Mos'r13 via the inverting amplifier circuit. Due to the modified circuit configuration, the effects of channel length modulation effects are compensated for, resulting in an ideal constant current source with high output resistance.

In addition, in the above example, the load N08T14 is E-M (J
Although ST is used, this may be DM (JS'l'), in which case NUST14 will have a configuration in which the gate and source are connected.Also, in order to reduce the voltage drop of the current source itself, MO8T14 The threshold voltage may be set to a value different from other M (JST) in the circuit.
This is possible by making the UST 14 a MO8'l' without the ion implantation process for controlling the threshold voltage. Furthermore, in the above embodiment, the amplifier circuit (!: E-, MUST12 and D-MUST
Although an inverter circuit consisting of ll is used, this is merely an example, and any of various well-known construction methods may be used for the inverting amplifier circuit.

As explained above, according to the present invention, the conventional N(JS
The disadvantages of the current source are eliminated and a current source with extremely high output resistance can be obtained, so the effect is great.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an example of a current source using a conventional MOS transistor, Fig. 2 is a percentage curve diagram showing an example of current-voltage characteristics of a MOS transistor, and Fig. 3 is a circuit diagram of an example of a current source using a conventional MOS transistor. It is a circuit diagram.

Claims (1)

[Claims] an inverting amplifier circuit, a first MOS transistor whose gate is led to the output of the inverting amplifier circuit and whose source is led to the input of the inverting N111m circuit; a source of the first MOS transistor and a DC power source; a second MOS transistor for load connected between the first Mo5i
A current source characterized in that the drain of a transistor is used as an output terminal.