JPS58156206A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an automatic gain control circuit due to a signal hit, by providing a switched capacitor circuit at the output side of an error detecting part of signal level in order to hold the control signal. CONSTITUTION:A full wave rectifier FWR and an operational amplifier OP2 perform the detection of an error between signal levels as well as the multiplication of the signal levels by obtaining the difference between the mean level of the output V0 of a lead 14 and the reference voltage REF and then multiplexing the loop gain to said difference. An integrator 111 has a switch to change over a capacitor CS by a clock fS and charges the control voltage on a lead 102 to the capacitor CS. The clock fS is set at O when the signal voltage V1 has a hit and stops the changeover of a switch SW. Therefore a capacitor C holds the voltae obtained immediately after the changeover of the SW, and the voltage of the amplification factor control signal VG is held as it is. The gain of a variable gain amplifier VGA is also kept as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit. In particular, a variable gain amplifier and an error detection circuit that generates a first signal indicating a difference between the output of the variable gain amplifier and a reference level;
The present invention relates to an automatic gain control circuit including a loop filter having an integrator that integrates a first signal to generate a second signal and controls the gain of a variable gain amplifier using the second signal.

Conventionally, in such automatic gain control circuits using analog circuits, the time constant of the integrating circuit included therein has been fixed to a constant value. Therefore, if for some reason no signal is present for a period longer than this time constant, the gain of the variable gain amplifier will fluctuate to a very large value. This often causes inconvenience in the following cases: For example, when such an automatic gain control circuit is used in a communication line receiving device, if there is a momentary interruption of the input signal that is longer than the time constant of the integrating circuit, the gain of the automatic gain control circuit will fluctuate to a very large value. However, when it receives the input signal again, it outputs a signal with a very high level. This phenomenon also occurs when reception is temporarily interrupted for transmission on a half-duplex line. In a two-wire half-duplex line, when transmission begins at the transmitting end, the automatic gain control circuit of the receiver at that transmitting end receives a high level transmission signal, so the gain of the automatic gain control circuit becomes extremely low. will be set low. In addition, in a demodulator that receives and demodulates data signals such as facsimile signals,
In order to adapt each device such as an automatic equalizer included in the demodulator to the line characteristics, prior to transmitting the data signal,
For example, a predetermined training sequence as defined in the International Telegraph and Telephone Consultative Committee (CCITT) Recommendations V, 27 BIS/LER and V, 29 is received. The automatic gain control circuit must respond quickly to the first alternation included in this training sequence, but not during steady-state conditions such as the binary random step that follows the alternation and the subsequent reception of the data signal. Then, we must avoid reacting to momentary noise that may be included in those signals. Therefore, such a gain control circuit is required to set the time constant of the integrator circuit short at the beginning of the training sequence to respond quickly, and to operate slowly by setting the time constant to a long time in steady state. be done.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to eliminate such drawbacks of the prior art and provide an automatic gain control circuit in which the time constant of an integrating circuit is variable.

Another object of the present invention is to provide an automatic gain control circuit that can maintain the gain.

These objectives are achieved by an automatic gain control circuit according to the invention as follows. That is, this automatic gain control circuit is inserted between a storage means for temporarily storing the level of the first signal, an error detection circuit and an integrator, and a first gain control circuit that connects the error detection circuit to the storage means. and a second state in which the integrator is connected to the storage means, the switching means making the frequency of switching between the first and second states variable. This makes the time constant of the integrator variable, and by stopping this switching, the gain of the variable gain amplifier is maintained.

Such storage means and switching means are realized by switching and switching.

Next, embodiments of an automatic gain control circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an example in which an automatic gain control circuit according to the present invention is applied to a demodulator that receives and demodulates a line signal such as a facsimile signal. In the same figure,
This demodulator includes a bandpass filter BPF connected to a terminal 10 for receiving a line signal from a communication line, and an automatic gain control circuit AGC connected to an output 12 of this filter BPF.
and a multiplier MLT1, one input of which is connected to the output 14 of the automatic gain control circuit AGC.

The other input 16 of this multiplier MLT 1 has an oscillator O
A low-pass filter LPF is connected to the output IS of the multiplier MLT1.

An automatic equalizer AAE is connected to the output 20 of the filter LPF, and has an output terminal 22 for generating an equalized data signal.

The details of the demodulator shown in FIG. 1 are omitted because they are not directly relevant to understanding the present invention. The line signal transmitted through the communication line is filtered by a filter BPF to remove unnecessary noise in the band.
The signal is kept at a constant level by the automatic gain control circuit AGC. This constant level signal is transmitted to the oscillator O8C and the multiplier M.
Equalizer A that is demodulated to a baseband signal by LT 1 and low-pass filter LPF and automatically adapts to the line characteristics.
The signal is equalized by the AE and output to the terminal 22 as an equalized analog data signal.

By the way, when such a demodulator first receives a data signal such as a facsimile signal, it is necessary to use a demodulator according to, for example, the International Telegraph and Telephone Consultative Committee (CCITT) Recommendation V, 27 big/l.
It is optimized by a predetermined training sequence defined by er and v, 29, etc. As is well known, the beginning of this training sequence is an alternation in which O and 1 symbols occur alternately, but the automatic gain control circuit AGC included in the demodulator quickly adjusts to the first symbol of this alternation. We must respond. ′
Therefore, in this case, the response time, ie, the time constant, of the automatic gain control circuit AGC needs to be shortened. Further, after the binary random step following this alternation, the time constant must be made long so that the automatic gain control circuit AGC does not respond to instantaneous noise contained in the line signal. This also applies to the data signal reception operation after the training sequence.

The automatic gain control circuit AGC shown in FIG. 1 has a function that satisfies such requirements, and the details thereof will be explained with reference to FIG. 2.

FIG. 2 is a circuit diagram showing details of the automatic gain control circuit AGC, in which a variable gain amplifier VGA is connected between leads 12 and 14 shown in FIG.

A full wave rectifier m is connected to the lead 14 and its output is 100
is connected to the inverting input (→
It is connected to the. The inverting input (-) of the amplifier OP2 is supplied with a reference voltage REF via a resistor RA2, and is also connected to the output 102 of the amplifier via a capacitor CA and a resistor αRA. The resistors RAI and RA2 have the same value, and the resistor α has a value α times the resistance value of the resistor RAN or RA2. Further, the non-inverting input (G) of the amplifier OP2 is grounded. These operational amplifiers OP
2. The circuit consisting of resistors RAW, RA2 and αRA, and capacitor CA is connected to the output 10G of full-wave rectifier m.
The capacitor CA also functions as a low-pass filter by adding the voltage V at and the reference voltage RgF and multiplying by the loop gain α.

Output 101 of operational amplifier opz! is analog switch S
W is connected to one contact 104, and the other contact 10
6 is connected to the inverting input ←) of opi of the operational amplifier. The inverting input ←) of the amplifier opi is connected to its output lO8 via a capacitor C, and the output 108 is connected to the gain control terminal of the variable gain amplifier VGA. The terminal 110 of the switch SW is connected via a capacitor C8. Grounded. As a result, switch SW and capacitor C8 constitute a "switched capacitor". Also operational amplifier opi.

An integrator 111 is formed by capacitors C and C8 and switch SW. This integrator 111 functions as a loop filter.

The control lead 112 of the switch SW is connected to the output of a frequency divider DIV, one input 114 of which is connected to the output of the AND dart 11g, and the other input 118
is supplied with a time constant control signal TC. AND goo) 1
A clock fc is supplied to one input 110 of 1g,
A hold signal HOLD is supplied to the other input 122 via an inverter 1a4. These hold signals HOLD.

Control signals such as the time constant control signal TO and the like are supplied from a training sequence control device (not shown). The frequency divider circuit DIV is a circuit that divides the frequency of the clock fc supplied to the input 114 to 1/11 and outputs the frequency f8 to the output 112. This frequency division ratio n is the time constant control signal of the lead 118. It can be changed by TC.

The analog switch SW performs a switching operation in response to a control signal f8 supplied to the lead 112. That is,
Capacitor C8 connected to terminal 110 of switch SW
is the inverting input (
→ or connected to the operational amplifier OP through contact 104
2 output 102, and this operation is performed at the frequency f
Repeat with 8. Therefore, the equivalent resistance R due to switching of this capacitor C8 at the frequency f8 becomes C8@f8. Therefore, the time constant T of the integrator 111 is C T = CR = η7. As mentioned above, the switching frequency f of the lead 112
Since 8 is the clock f divided by n, f8=fc/n, and therefore the time constant T of the integrator lit is nT=-C8@fc. Since the division ratio n is variable by the time constant control signal TC, the time constant T of the integrator 111 is changed by the time constant control signal T.
It can be changed by C.

To explain the operation, the full-wave rectifier is a variable gain amplifier V
Output voltage V at output 14 of the GA.

is full-wave rectified and its negative half-wave V is output to the lead 100, resulting in Vo=l VI I. As mentioned above, capacitor CA functions as a low-pass filter, and this voltage
It acts to remove the alternating current component.

Therefore, it functions as part of the loop filter of the AGC loop. The operational amplifier OP2 adds the voltage of the lead 100 and the reference voltage REF, and outputs the result obtained by adding the loop gain α to the output 102 as the voltage v2. Therefore, this circuit has an output voltage V on lead 14. It has a signal level error detection and multiplication function that calculates the difference between the average level of and the reference voltage REF and superimposes the loop gain α on the difference.

The voltage v2 of the lead 102 is equal to the frequency f8 of the lead 112.
It is integrated by an integrator 111 having a time constant T determined by the amplification factor control signal ■ to the lead lO8. The output will be closed. The summing gain amplifier VGA receives an amplification factor control signal ■. The gain increases as the voltage increases. Suppose that the gain of the gain amplifier VGA is too high and the output V.

If the average level of is greater than the reference level REF', the output voltage v2 of the operational amplifier OP2 becomes positive, and as a result of being integrated by the integrator 111, the amplification factor control signal V. The voltage of VGA gradually decreases, which causes the gain of variable gain amplifier VGA to gradually decrease. In the opposite case, the operation is reversed, and the gain of the amplifier VGA gradually increases. l
, Therefore, this automatic gain control circuit AGC controls the output voltage so that the voltage V2 becomes 0, that is, the output voltage ■. The gain of amplifier VGA is controlled so that the average level of is equal to reference level REF.

By the way, since the holding signal HOLD is normally logic "0", the clock fc passes through the AND gate 116, is divided by the divider DIV, and is supplied to the switch SW as a frequency of 18. However, when the hold signal HOLD becomes a logic "1", the level of the input 122 of the AND gate 116 becomes a logic "0" by the inverter 124, so that the clock fc is not supplied to the frequency divider DIV. Therefore, the switch SW also stops the control signal fs, which causes the analog switch SW to connect the capacitor C8 to the contact 104 or
It will stop while connected to 06.

Therefore, the voltage across capacitor C is V immediately after that.

continues to maintain a charged state at the level of Therefore, the voltage of the amplification factor control signal v6 is fixed at that state, and the gain of the variable gain amplifier VGA is maintained as it is. This essentially corresponds to the switching frequency f8 becoming 0 and the time constant T of the integrator 111 becoming infinite.

Although the automatic gain control circuit according to the present invention has been described in terms of the particular embodiment illustrated, the invention is not necessarily so limited. For example, a power calculator, a half-wave rectifier, a peak detector, etc. can be used instead of the full-wave rectifier m.

If the switching frequency 18 of the analog switch SW is sufficiently higher than the Luso signal frequency of the automatic gain control circuit AGC, the low-pass filter characteristic provided by the capacitor CA is not necessarily required. However, if this is not the case, i.e. if the signal frequency is close to the switching frequency f8 of the analog switch SW, this low-pass filter characteristic is necessary to avoid aliasing caused by sampling the voltage v2 by the switch SW. It is. Note that this low-pass filter may be a first-order filter as in the illustrated embodiment, but a higher-order filter may also be used. Also, each resistor RA
I-RA! , αRA, etc. can also be replaced by switched capacitors.

By configuring the automatic gain control circuit according to the present invention in this manner, it can be effectively applied to a demodulator for facsimile signals, for example. For example, in a training sequence, the time constant of the integrator can be set small in the alternation to obtain quick tracking performance, and the time constant can be set large in the subsequent steady state to obtain high stability. In response to momentary interruptions, the gain can be maintained by stopping the switching clocks of the switched capacitor and the mother capacitor, so that malfunctions of the automatic gain control circuit due to momentary interruptions can be minimized. Furthermore, when restarting after interrupting reception, the gain immediately before the interrupt can be maintained, so the time conventionally required for the automatic gain control circuit to follow the restart can be eliminated. In addition, since the resistor that determines the time constant of the integrator is realized by a switch and a chitocanal detector, an automatic gain control circuit suitable for integrated circuits, particularly MO8 integrated circuits, is provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a demodulator to which an automatic gain control circuit according to the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of the automatic gain control circuit according to the present invention. Description of symbols of main parts C8... Capacitor DIV... Branch m... Full wave rectifier OPI, OP2... Operational amplifier SW... Analog switch VGA... Variable gain amplifier 111... Integrator patent applicant Ricoh Co., Ltd.

Claims (1)

[Claims] A variable gain amplifier; a first device indicating a difference between the output of the variable gain amplifier and a reference level;
an error detection circuit that generates a signal; and a loop filter that has an integrator that integrates the first signal to generate a second signal and controls the gain of the variable gain amplifier using the second signal. The automatic gain control circuit includes: storage means for temporarily storing the level of the first signal; and the error detection circuit and the integrator. switching means for selectively selecting a first state in which the integrator is connected to the storage means and a second state in which the integrator is connected to the storage means; An automatic gain control circuit characterized in that the time constant of the integrator is made variable by making the frequency of state switching variable, and the gain of the variable gain amplifier is maintained by stopping the switching.