JPS58134342A - External interrupting device - Google Patents

Abstract

PURPOSE:To decrease the number of ports down to half and to realize a compact package, by transferring an external interruption factor by a pseudo bidirectional port and at the same time resetting the external interruption factor through the same port. CONSTITUTION:The signals of external interruption factors I0 and I1 are applied to each clock pulse CP terminal of flip-flops 40 and 41. Thus an external interruption input signal INT is produced to be applied to a CPU1. The CPU1 accepts an external interruption with the signal INT and reads the levels of output terminals A0 and A1 of switching circuits 50 and 51 through two pseudo bilateral ports 2 and 3. The CPU1 performs an external interruption process in terms of software and switches the ports 2 and 3 to an output mode. Thus both ports 2 and 3 deliver ''0''. As a result, the flip-flops 40 and 41 are perfectly reset, and the CPU1 prepares for acceptance of the next interruption signal.

Description

[Detailed description of the invention] [Technical field of the invention] The non-invention is the external interrupt Mi in the microcomputer 62.
Regarding lEC.

[Technical background of the invention]

When processing multiple external interrupt factors in a microcomputer system, one external interrupt source line and the same number of external interrupt factors as the maximum number of factors are used to identify the external interrupt factors. It is common practice to use an input-only port and use another port as an output-only port to handle external interrupts.

[Trends in background technology]

In the above case, the number of external interrupt factors is the total number of external interrupt factors and the number of external interrupt factor reset signals (usually twice the maximum number of external interrupt factors). As the number of factors involved increases, the number of 8T boats required increases, which not only makes it difficult to make the package smaller and more compact.

Expansion of external interrupt factors causes problems. [Purpose of the invention] The present invention has been made in view of the above points.

It is possible to reduce the number of boards used for external MB by half and make the package smaller and more compact. It is an object of the invention to provide a portable external interrupt device. [a] In order to achieve the above object, the present invention provides that a microcomputer is provided with one or a pseudo-bidirectional boat that has the functions of both an input port and an output port.
Utilizing this pseudo-interactive boat I can create a 1. 'l1
1. The circuit configuration is such that the external interrupt factor ycP (J1) is transferred and the reset signal for resetting the external interrupt factor Y is output from the same boat to the outside. The number of boats that are no longer in use has been significantly reduced, allowing them to be used for other purposes.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the - side.The external interrupt device shown in the figure shows a circuit example in which there are two external interrupt factors. The computer CPU 1 has a plurality (in this case two) of pseudo-bidirectional ports z, xyit that can serve as input, output, and both functions and at least one external interrupt input signal. INT is input to the above port I. The output side of the output buffer Qn and the input side of the input buffer Ill, which is driven in the input mode IN, are wired-OR connected. ＃、'
F is a flip-flop that is cleared (set to !1) when the external interrupt factor l is □. 5 is composed of a resistor R and a transistor Q@@-2, and the output Q of the flip-flop 4°
This is a switching circuit controlled by Fujitsubu flop 4.c, which is turned off when there is an external interrupt factor Io and the flip-flop 4. is set, and when there is no external interrupt factor Io, the flip-flop 4. Or a feeling of being on when being reset;
The output terminal A of this switching circuit 6 is connected to the pseudo-bidirectional port 2, and 6 is a monostable multivibrator to which the output terminal 6 of the switching circuit S is connected; This detects the falling level of the output terminal of the switching circuit 5 from the output C from the IITJ board I and generates a reset signal with a constant width determined by the internal timer circuit I: υR. Is it the logical sum of system reset No. 1♂ and the reset signal from the above metastable multivibrator? This is an OR circuit which supplies the output to the clear terminal of the flip-flop 4.

Similarly to the board 2 described in 1, the fold-like dual-universal board 3 also has an output transistor Q1 and an input buffer 1B. Similarly, a flip-flop 4, a switching circuit 51, a monostable multivibrator 61, and an OR circuit OR3 are provided in response to the external interrupt factor 11. OR of Q output, that is, external interrupt factor l@.

! , and the OR circuit OR (:Therefore, a signal generation circuit 1 is provided which generates an external interrupt input signal INTV to the CPU 1.Next i:, Operation of the external interrupt device with the above configuration [Explanation] The CPU 5 always sets the initial state of each boat 2.1 to the input mode ≦: ・Here, the input mode is the output idle sister ・e Q * @ or OFF state 0 First, external interrupt factor 1 For example, if ., I, -10,000 occurs, two C will be used to explain that the clock terminal CP of the flip-flop 4 is given a signal of the external gill J factor l; The flip-flop 4 is set by one of the signals, and the output Q is a low level "L".
(Q becomes high level 1H,') - Since the flip-flop 41 remains in the reset state, its output Q remains high level "H" (Q remains low level °L). As a result, CPUI
An external interrupt input signal INT is generated.In this state, the output terminal A of the switching circuit 5 is such that the output transistor Qo is off and the output Q of the Fujitsubu flop 4 is at a low level. Since the transistor Qol is off due to the low level (7), the C2 high level is 1H', and the switching circuit 5. output end A.

is Fujitsubu flop 4. Output Q is high level @H”
Therefore, the transistor Q11 is in the on state, so it is at low level @L" ・The above external interrupt manual signal I Reperun connection of output end A・・AH of switching path 50m1% to both same-sex boat 2.3,
engulf it. CPUI7 outputs these #l! A o a
A 1 level χ each person's buffer lHv*lJ
i' can be read correctly. The CPU reads the high level °H''l of the output terminal A0, and based on this, executes the preset external interrupt processing, then switches the bidirectional baud)jv output mode to output '0#Y'. This output mode weight: is the output transistor Qao
is turned on, and the output terminal A of the switching circuit 5 connected to the boat 2 changes from high level "H" to low level'
Shift to L”/Therefore.

In response to this falling level change, the double-stable multivibrator 6 maintains a high-level reset signal Bo for two periods.
't' generated This reset signal B is OR circuit OM
The flip-flop 4 is reset via e. As mentioned above, after the CPU 7 has set the baud to the baud mode, the CPU 1 receives the next interrupt signal from the external interrupt factor I in preparation for receiving it. I: pseudo-bisexual bo)jV#
Set to pfi input mode - This 6: One output meter,
1. ．． Transistor 1 is turned off and the primary external interrupt factor can be latched. External interrupt factor 1. ．． I will explain the case where there are both 4-external interrupts (first, baud) J
Is is in the input mode, and the output transistors Q0 and eQle are off.Next, each flip-flop, . At the leading edge of each signal, the flip-flops 4. and 4% are set, and their outputs Q become low level "Lo".

As a result, an external interrupt signal INT to the CPU J is generated by the output 5 of the OR circuit OR. In this state,
Transistor 1...Q @ @ hQ*, Qlm are common; output terminals A, , A are both connected to g2.
DCPUI, which is 11#, is the interrupt input signal I.
When CPUJ accepts an external interrupt via NT, it passes through two pseudo-bilateral ports 2.3f to switching circuit 5o.

5, the level of the output terminal Ao+At continues, and the CPU 1 is connected to the level of the output terminal Ao+At of the output aAssA1.
oCPTJt that can continue correctly is output terminal A.
, , A, after incorporating the high level °H” 'k fA,
External interrupt processing with the interrupt priorities of external interrupt factors ■ and II preset. ．． S and C: °01v output, this is the same; therefore, the output transistor is also turned on, and baud) J#JJ
Two connected switching circuits5. ,! , the output end A・
.

As) i Both c high level @H” to low level 1L
6. Move to this output terminal. The level changes of A, are detected by the monostable multivibrators 6, 6S, respectively, and the reset signals B,, B, of high level @h' are output for a short period of time from the monostable multivibrators 6, , -. Koto C; becomes this reset signal B et
s, corresponds to the OR circuit OR@, UR@t'
After flip-flop 4. , 4. tReset・Then, the CPUI.

) z j s v Input mode d: Yes, this is true; Therefore, the output transistor Qa * -Q@ is in the off state I:
1 state in which the external interrupt factors can be latched C 2 - Here, if the above-mentioned external interrupt factors exist at the same time, in what priority order should these external interrupt factors be implemented? , or after processing one external interrupt source,
The details of external interrupt processing, such as whether or not to process other external interrupt factors subsequently, are handled by software. If you do this, you can freely process four external interrupt factors using software. It can be modified and extensibility is extremely high.

In addition, in the above embodiment, the reset (
d No.B*Btt' is intended to be generated, so the entire circuit is not integrated.

It can be easily realized by combining discrete type circuits that are configured independently. In the above embodiment, there are two external interrupt factors. 6
Yutsui-Cwa1,1.・、-71、Ah、yo、When processing a large number of external interrupts or more, the 0 or 1 circuit itself can be implemented with either an MO8 transistor or a pie hole transistor circuit element. [Effects of the Invention] According to the present invention, there is a circuit configuration in which a pseudo-bisexual baud) Y is used to transfer to an external interrupt factor vCPυ, and the same baud) is used to reset the external interrupt cause ''. As a result, not only can the number of boats used be halved, making the package smaller and more compact, but also the boats that are no longer in use can be used to expand external interrupt devices or for other purposes.
2. Provides an external interrupt device that can be used to realize a highly flexible microcomputer.

[Brief explanation of the drawing]

The second aspect is the circuit configuration of the external interrupt gIIi according to the first embodiment of the present invention. l...CPU, j, 1...Pseudo bidirectional port. □・1・1 46*4@ ・・・F□nee, :1. Whirl flop, 5
・ , 5. ...Switching oil path-6・ , 6.・・・
・A stable multi-vibrator! ...Individual number generation circuit,
Q...1・Q,...output transistor, Q・-0
Q, 1... Transistor, IB, , IB,... Input buffer, R..., RI... Resistor, / u R, uR0
*OR,・”11 circuits, INT,...External interrupt input signal, 1゜all...External interrupt device Q External agent Patent attorney Hiko Suzuki

Claims (1)

[Claims] The central processing fMI device has a similar twin-universal boat 8 and at least one external interrupt human-powered signal line controller Y [the number of external prints for the microcomputer to detect a plurality of external imprinting factors. The flip-flops and the interrupt factor detection outputs from these flip-flops are logically ORed and the central part #! a signal generation circuit for generating an external interrupt input signal to the device; and the plurality of pseudo-bipods;
A plurality of switching circuits whose output terminals are connected to each other and which receive the outputs of the plurality of flip-flops and which change states depending on the presence or absence of an external factor; Detects each predetermined change in the output level of the switching circuit and resets each corresponding flip-flop) to generate a 4H signal.
Equipped with a low-stable multivibrator of Yokuei, when using the same pseudo-bidirectional baud)Y to transfer the external interrupt factor to the central processing unit Wt, the external interrupt factor is reset from the two central processing units. An external interrupt device kt characterized in that m= is configured to do so.