JPS581319A - Switched capacitor type electronic circuit - Google Patents

Abstract

PURPOSE:To fix the transfer characteristics of a switched capacitor type electronic circuit on the basis of a frequency division ratio logically determined by varying a period when a sitch is turned on and off at the same rate for every switch through a clock frequency divider. CONSTITUTION:Switches 5 and 6 are controlled by clock pulses of frequency fc generated by a clock generator 14, and swichers 8 and 9 are controlled by pulses of fc/N obtained by passing said pulses through a clock frequency divider 15. Therefore, the equivalent resistance Rs of the circuit consisting of the switches 5 and 6 and a capacitor 10 is 1/fcCs, and the equivalent resistance Rf of the circuit consisting of the switches 8 and 9 and a capacitor 12 is N/fcCf. Consequently, the circuit shown in the figure has such transfer characteristics that V2/V1=Rf/Fs=NCs/Cf, and they are fixed by selecting the capacity ratio of those two capacitors and the frequency division ratio of the frequency divider. In addition, when the capacity ratio of the capacitors is set to 1, the transfer characteristics depend only upon the frequency division ratio of the frequency divider.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switched capacitor type electronic circuit comprised of switches, capacitors, operational amplifiers, and the like.

First, we will explain the principle by which a general switched capacitor can be regarded as an equivalent resistance.

The basic configuration is shown in Figure 1. In Figure 1, 3 is the period Tc
4 is a capacitor with a capacitance value C, l is an input terminal for voltage η, and 2 is an output terminal for voltage V.

At time t; OVc, the capacitor 4 is charged from the input terminal 1 so that the charge becomes α, and then at time t-Tc,
/2, the capacitor 4 is discharged so that the charge becomes G.

Therefore, the amount of charge applied from the input terminal 1 to the output terminal 2 with respect to the clock period Tc during which the switch reciprocates is ΔQ x c(v, −V, ).

Therefore, the average current I flowing during the period Tc is: 1-Q/Tc-0(v, v*)4°=C(u drawn)fc where the switching frequency ``'/Tc.

Therefore, the equivalent resistance is, and is inversely proportional to the capacitance value of the capacitor and the switching frequency.

A prior art switched capacitor amplifier based on this principle is shown in FIG. 5, 6, 8 in Figure 2.
9 is a switch constituted by M) 8 FBT, 10 is for input; It has the opposite effect. 14 is a clock generator with frequency fc, and 7 is a charge absorbing capacitor.

The operation of this amplifier will be explained below. switch 5 is on,
When the switch 6 is off, the capacitor 10 is charged from the input voltage η. When the switch 5 is off and the switch 6 is on, the input terminal of the operational amplifier 11 can be regarded as a virtual ground due to the action of the operational amplifier 11, so all of the charge is transferred to the capacitor t7. Switch 8 is also off.

When switch 9 is on, output voltage η is applied to capacitor 1.
When the switch 8 is turned on and the switch 9 is turned off, all of the electric charge is transferred to the capacitor 7. However, if the nine lever operations are repeated, an equivalent resistance will be obtained by the above-mentioned switch and capacitor.

In other words, switch 5.6. Equivalent resistance Rs consisting of capacitor 10, switches 8, 9 . It can be regarded as a superior abrasive resistor Rf consisting of the capacitor 12. As a result, this amplifier can be equivalently regarded as an operational amplifier with an input resistance Rs and a feedback resistance I'Lf, and its transfer characteristic is approximately expressed by an operator representing the frequency, where 8 is an operator representing the frequency. /2πC, Rf, which is determined by the ratio of the two capacitors.This is advantageous when constructing this amplifier with an integrated semiconductor device.Easier than MO8FIT K The accuracy of the capacitance ratio Cs/Cf is good because the switch can be configured and the manufacturing process is a batch process using a photomask.Therefore, the transfer characteristics of the amplifier can also be manufactured with high precision and the performance is good, especially when using 'MDS type integrated semiconductors. Since the resistance element occupies a relatively large area in a device, using an equivalent resistance consisting of a switch and a capacitor can reduce the integrated area.
It's also economical.

However, this accuracy is good only when Cs/Cf is close to 1. Therefore, for example, when k is Cs/Cf-1α, ten capacitors having the same shape as Cf are provided, and these are connected in parallel and used as Cm to improve accuracy. However, as a result, the accumulation area increases,
The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art and provide a high-performance amplifier that is economical and has good precision. There is K.

The present invention is characterized in that, in the equivalent resistance composed of the switch and the capacitor, a desired resistance value is not obtained from the capacitance ratio of the capacitors, but from a logically determined clock frequency.

Embodiments of the present invention will be described in detail below with reference to FIG.

The same parts as in Diagram 2 are given the same numbers. 15 is shown as a four-way frequency divider, which produces a pulse every K1 times the pulses from the clock generator 14.

That is, a clock pulse of frequency fc is input, and a clock pulse of frequency fc is output. Also switch 8
And 9 is frequency division lol! 15, and switches 5 and 6 are controlled by the output of the four-stroke generator 14. Therefore, switches 5, 6 . The transfer characteristics of the device are the equivalent resistance 9 consisting of a capacitor ytlo and the equivalent resistance Rf consisting of a capacitor 12. Under the same conditions as described above, the necessary transfer characteristics can be easily obtained by selecting the capacitance ratio of Denna and the division ratio of the frequency divider. be able to. Here, if the capacitance ratio 0s10f is selected as 1:IK, which has the least manufacturing variation and the highest precision, the transfer characteristic is determined only by the frequency division ratio. In other words, since the division ratio is determined logically and has no errors, extremely high precision characteristics can be obtained. Furthermore, if the clock frequency divider consisting of a logic tree is constructed using an integrated semiconductor device, this problem does not arise because it can be realized with a small occupied area.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. ll
The same parts as in Figure X3 are given the same symbols. 18 is a new frequency divider with a frequency division ratio M; M)8 Flipl mill switch in which the frequency dividers 5 and 6 are controlled by the output of the frequency divider 18;

In the circuit configuration shown in FIG. 4, if the capacitance ratio of the capacitors IO and 12 is set to 1:1, which gives the best accuracy, it is clear that the transfer characteristic of the amplifier becomes η N /V,−/M. This not only makes the transfer characteristics more accurate, but also has the advantage of increasing the degree of freedom in design since it is determined by the frequency division ratio of the two dividers.

FIG. 5' is a circuit diagram showing an embodiment in which the present invention is applied to an adder. The same parts as in FIGS. 3 and 4 are given the same reference numerals. 21 is an input capacitor 18.22 is a divider with a dividing ratio M s Ml, and 5.6 and 19.20 are switches each controlled by the output of the divider 18.21. Considering the same operation as described above, it is clear that the output of this adder is T, -M, V, and ten lines. However, the ratio of the three capacitors is selected to have the highest accuracy (Cs: Cs+: Cfwl: 1: 1).

This constitutes an adder that adds inputs v1 and V with weights M and stripes. Since the weight M and the stripes are determined logically, the accuracy is extremely high.

In the above explanation, it is assumed that all capacitors are equal and have a ratio of 1, but for example, in the embodiment shown in FIG. 3, the transfer characteristic V* /V, K, which is -100, is the frequency division ratio N, which is 10. It is clear that it is also possible to use a combination as in the case of the capacitance ratio Cs/Cf (10), as long as the accuracy of the capacitance ratio does not deteriorate. Further, if the amplifier is configured using a variable frequency division ratio type that changes the frequency division ratio by a control signal such as a voltage value as a clock frequency divider, the transmission characteristics can be easily controlled by controlling the frequency division ratio. Using this amplifier, automatic gain control circuits and the like can be easily configured.

As described above, according to the present invention, in a switched capacitor type electronic circuit, the cycle of the reciprocation of the switch is determined logically by using a clock frequency divider for each switch and varying it by a certain ratio. The frequency division ratio can determine the transfer characteristics of the circuit. Therefore, it is possible to reduce or eliminate variations in transfer characteristics due to variations in capacitor manufacturing, which are the disadvantages of the prior art, and it is possible to obtain product uniformity and improve yield, making it more economical.

[Brief explanation of drawings]

Figure 1 shows the switch), -? Diagram explaining the principle of Yabashita circuit,
FIG. 2 is a circuit diagram showing a conventional switched capacitor amplifier, and FIG. 3 is a switched circuit diagram showing one implementation example of the present invention.
FIG. 4 is a circuit diagram of a capacitor amplifier, FIG. 4 is a circuit diagram of an amplifier showing another embodiment of the invention, and FIG. 5 is a circuit diagram of a switched toe capacitor adder showing still another embodiment of the invention. 22 human power capacitors 2: Feedback capacitors 5, 6, 8, 9: Switch 11: Operational amplifier 14: Four-wheel generator 15, 18, 22: Frequency divider 1 Figure 3 Figure

Claims (1)

[Claims] 1. In a switched capacitor type electronic circuit including a plurality of equivalent resistances each consisting of a switch and a capacitor, a clock generator for controlling switching of the switch and a clock generator for controlling the frequency of the output of the clock generator are provided. 1. A switched capacitor type electronic circuit comprising a plurality of dividers for dividing stations and a plurality of switches controlled by the output of the frequency divider. 2. In a switched capacitor type electronic circuit that includes a plurality of equivalent resistances each consisting of a switch and a capacitor, a block generator that controls switching of the switch and a plurality of dividers that divide the frequency of the output of the clock generator are provided. , a plurality of switches controlled by the output of the frequency divider. A switched capacitor type electronic circuit characterized by comprising a frequency divider that controls a frequency division ratio by a control signal.