JPS5813050A - Packet reception and storage system - Google Patents

Abstract

PURPOSE:To prevent the ineffective pending of the PM (packet storage memory) of a stand-by system CCE (communication controller) by allowing an interruption from the CCE to a CPU after confirming that packets are transferred normally from the CCE to the PM. CONSTITUTION:On receiving packets from a circuit, a CCE stores some of them in a PM and also transfers the remainder to a CPU, which is then informed of the reception together with PM addresses wherein the packets are stored. The CPU receives the packet reception report from the CCE to confirm that packets are stored in an MM (main memory), and then instructs a PWC (PM storage control part) to store the packets from the stand-by system CCE in the PM. The PWC transfers the packets stored in its own PM to the PM of the stand-by system CCE. After confirming that the transfer is carried out normally, the CCE causes an interruption to the CPU, thereby informing the CPU that the transfer to the PM of the stand-by system CCE ends.

Description

[Detailed Description of the Invention] The present invention is applicable to a packet transmission/reception method for packet switching.
The present invention relates to a method for receiving and storing packets in a multiplexed communication control unit (ccm), packet storage memory (PM), and central geographic unit (CPU) and main memory (m).

The first wA is a block diagram showing the configuration of CCl1i and CI"U.CPtI is the central control unit (CC) and MMK.
Please be prepared, CCI afuu 71 transfer 111u control 1l (IITc), PM.

Line control @ (LCT) and rounded PM storage control 1 to implement the present invention! (PWC) is configured. Note 1! l, L 4 are MV-CC, CC-1 respectively
1'rC, IITC-PM.

This is a line that connects 1'rc and LCT and transmits and receives information between the scissor-connected components. In the following explanation, the transmission and reception of information relating to each component is performed via the lines.

In the JII1 diagram, when a packet is received from the CCI dl line, 70 parts are stored in the PM and the other part is transferred to the cpv. cpv stores the received packets, performs router sensing, etc., and then transfers the packets back to CCIC. When ccm receives the transferred 9 packets from the CPU, PMPiK stores the packets stored in PMPiK. The armpit packet F is sent from the CPU to the designated line.

Normally, the CCE is 8-layered], and when a failure occurs, device switching is performed to prevent interruption of wICC1i8 processing. However, when device switching is performed, if there are no packets in the OPM within the CCE that has become active after switching, it becomes impossible to send the packets to the line.

For this reason, when packets are received in the CCG and stored in the PMIIC, packets are also stored in the PM of the CCG (backup system) to prevent packets from being lost when devices are switched. However, conventionally the backup system ccyt: OP
Since the process of storing packets in M is performed independently of the CPU operation, the CP
There are cases where packets are lost while being transferred to υ.

For example, if the CCE stores a part of the packet in the PM of the standby system CCM, and then a failure occurs in the active system CCI K and the device is switched, the other part of the packet that has not been transferred to the existing CPU in CCl3 may be lost. becomes. In this case the CPU
In this case, it is slow to detect that the packet has been received, and therefore it is not sent to the line.The PM packet is also not sent to the line forever, and the PM is held invalid.

One object of the present invention is to improve the above-mentioned drawbacks and eliminate the suspension of PM invalidation.

An embodiment of the present invention will be described below with respect to the l11 plane.

In FIG. 1, when the ccm receives a packet from the line, it stores part of it in the PM, transfers the other part to the CPU, receives the packet to the K CPU, and reports the fact along with the PM address where the packet was stored. During this time, the PWCH backup system CCI (2) does not deliver PM packets Om. After receiving the packet reception report from the CCE and confirming that the packet is stored in the deer, the CPU instructs the PwcK to store the packet in the standby CCI oPM. When the PWC receives this command, it
The packet containing the PMK is sent to the standby CCI OPM.
Transfer to. Furthermore, ccic HkoO transfer is normal KQ
After confirming that the error occurred, I decided to interrupt the CPU! j) Transfer 0 to the standby CCEOPM to the CPU and report that it has completed 90. 6. At the time of 5-but transmission, the CPU transfers the PM address where the packet to be combined is stored to the CCE along with the sending packet, Both data are combined in the ccg and sent to the next line.As shown above, the PWC for carrying out the present invention stores the packets in the standby system PM. Illustrating an instruction sequence.

As explained above, according to the present invention, invalid suspension of the CCI OPM can be prevented. This has the advantage that it can be prevented from being regulated by the government.

[Brief explanation of drawings]

FIG. 1 is an example of the block configuration of the CPU and CCI, and FIG. 3 is an example of each instruction sequence between the CPU and 001 according to the present invention. cpυ...Central processing unit, CC, -Central control unit, dish...Main memory, CCIc...Communication control unit, PM-
Packet storage memory, BTC-P4 transfer control unit,
pwc-PM storage control unit, LC〒-fighting system line, 1-・
Wire connecting between MM and C0, connecting between 5-cc and yttc: 6 wire, connecting between 5-ntc and pM & connection f h'l
1li, 4 = Il? A line that connects C and LCT. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (1)

[Claims] After the octuplic communication control device receives a packet from the line, a part of the packet is stored in the 0-packet storage mailbox for both the active and standby systems, and the other part is transferred to the central sensing layer device, and the packet is At the time of transmission, the two packets are combined in the overload control device and sent to the line.In the packet transmission/reception method, the communication control device determines whether the central processing unit KsIPv'h receives the packet and sends it to the line. Also, a means for writing the packet after the reception is confirmed in the packet storage mail of the standby system, and a means for interrupting the central processing unit after the writing is completed, is provided to perform 'Ik' from the nine configuration. A packet reception storage method characterized by: